Re: kern/57515: sparc32 GCC defaults to SC memory ordering, which is not true on SPARCv8 processors

[Koakuma <koachan+netbsd%protonmail.com@localhost>]

Martin Husemann wrote:
> Well, I don't know about v8 and early details, but kinda assumed it
> would be similar to v9 where it is under (kernel's) software controll
> (and binaries get run with the memory model they are compiled for).

Even if it works that way, v8 and v9 does not have sequential consistency
as a supported memory model, so binaries targeted for v7 might still run
wrongly on later processors anyway.

Taylor R Campbell wrote:
> That's an option too, but I bet it could be made to work reasonably
> well with a small tweak to gcc so that NetBSD can ask for -mcpu=v7
> -mmemory-model=tso instead of having -mcpu=v7 ignore -mmemory-model,
> if someone is willing to do the work and testing for it.

I just made this small patch that removes all the conditionals for
barrier instructions (except for `stbar` and `membar` since those are
not available in v7) and changes the default memory ordering to TSO.
Seems to get it to emit the proper barriers for me, but probably could
be done a little bit better, since I am not familiar with GCC internals.

diff --git a/external/gpl3/gcc.old/dist/gcc/config/sparc/predicates.md b/external/gpl3/gcc.old/dist/gcc/config/sparc/predicates.md
index 42316adc9..a743f1caa 100644
--- a/external/gpl3/gcc.old/dist/gcc/config/sparc/predicates.md
+++ b/external/gpl3/gcc.old/dist/gcc/config/sparc/predicates.md
@@ -78,6 +78,11 @@
 (define_predicate "const_double_or_vector_operand"
   (match_code "const_double,const_vector"))
 
+;; Return true if OP is Zero.
+(define_predicate "zero_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) == 0")))
+
 ;; Return true if OP is Zero, or if the target is V7.
 (define_predicate "zero_or_v7_operand"
   (and (match_code "const_int")
diff --git a/external/gpl3/gcc.old/dist/gcc/config/sparc/sparc.c b/external/gpl3/gcc.old/dist/gcc/config/sparc/sparc.c
index 7cfa9f806..c64127bc1 100644
--- a/external/gpl3/gcc.old/dist/gcc/config/sparc/sparc.c
+++ b/external/gpl3/gcc.old/dist/gcc/config/sparc/sparc.c
@@ -2009,7 +2009,7 @@ sparc_option_override (void)
       else if (TARGET_V8)
 	sparc_memory_model = SMM_PSO;
       else
-	sparc_memory_model = SMM_SC;
+	sparc_memory_model = SMM_TSO;
     }
 
   /* Supply a default value for align_functions.  */
diff --git a/external/gpl3/gcc.old/dist/gcc/config/sparc/sync.md b/external/gpl3/gcc.old/dist/gcc/config/sparc/sync.md
index 096372c09..ee85a653c 100644
--- a/external/gpl3/gcc.old/dist/gcc/config/sparc/sync.md
+++ b/external/gpl3/gcc.old/dist/gcc/config/sparc/sync.md
@@ -25,7 +25,7 @@
 
 (define_expand "mem_thread_fence"
   [(match_operand:SI 0 "const_int_operand")]
-  "TARGET_V8 || TARGET_V9"
+  ""
 {
   enum memmodel model = (enum memmodel) INTVAL (operands[0]);
   sparc_emit_membar_for_model (model, 3, 3);
@@ -36,7 +36,7 @@
   [(set (match_dup 1)
 	(unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
 		    UNSPEC_MEMBAR))]
-  "TARGET_V8 || TARGET_V9"
+  ""
 {
   operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
   MEM_VOLATILE_P (operands[1]) = 1;
@@ -49,7 +49,7 @@
 ;; ignore all such barriers on Sparc V7.
 (define_insn "*membar_empty"
   [(set (match_operand:BLK 0 "" "")
-	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
+	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_operand")]
 		    UNSPEC_MEMBAR))]
   ""
   ""
@@ -76,7 +76,7 @@
 (define_insn "*membar_storeload"
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
-  "TARGET_V8 && !TARGET_LEON3"
+  "!TARGET_V9 && !TARGET_LEON3"
   "ldstub\t[%%sp-1], %%g0"
   [(set_attr "type" "multi")])
 
@@ -262,7 +262,7 @@
    (match_operand:SI 1 "memory_operand" "")
    (match_operand:SI 2 "register_operand" "")
    (match_operand:SI 3 "const_int_operand" "")]
-  "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
+  "!sparc_fix_ut699"
 {
   enum memmodel model = (enum memmodel) INTVAL (operands[3]);
 
@@ -278,7 +278,7 @@
 			    UNSPECV_SWAP))
    (set (match_dup 1)
 	(match_operand:SI 2 "register_operand" "0"))]
-  "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
+  "!sparc_fix_ut699"
 {
   if (sparc_fix_gr712rc)
     return ".align\t16\n\tswap\t%1, %0";
diff --git a/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md b/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md
index 42316adc9..a743f1caa 100644
--- a/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md
+++ b/external/gpl3/gcc/dist/gcc/config/sparc/predicates.md
@@ -78,6 +78,11 @@
 (define_predicate "const_double_or_vector_operand"
   (match_code "const_double,const_vector"))
 
+;; Return true if OP is Zero.
+(define_predicate "zero_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) == 0")))
+
 ;; Return true if OP is Zero, or if the target is V7.
 (define_predicate "zero_or_v7_operand"
   (and (match_code "const_int")
diff --git a/external/gpl3/gcc/dist/gcc/config/sparc/sparc.c b/external/gpl3/gcc/dist/gcc/config/sparc/sparc.c
index 7cfa9f806..c1d89d8df 100644
--- a/external/gpl3/gcc/dist/gcc/config/sparc/sparc.c
+++ b/external/gpl3/gcc/dist/gcc/config/sparc/sparc.c
@@ -2009,9 +2009,9 @@ sparc_option_override (void)
       else if (TARGET_V8)
 	sparc_memory_model = SMM_PSO;
       else
-	sparc_memory_model = SMM_SC;
+	sparc_memory_model = SMM_TSO;
     }
-
+  abort();
   /* Supply a default value for align_functions.  */
   if (flag_align_functions && !str_align_functions)
     {
diff --git a/external/gpl3/gcc/dist/gcc/config/sparc/sync.md b/external/gpl3/gcc/dist/gcc/config/sparc/sync.md
index 096372c09..97c83f8f7 100644
--- a/external/gpl3/gcc/dist/gcc/config/sparc/sync.md
+++ b/external/gpl3/gcc/dist/gcc/config/sparc/sync.md
@@ -25,7 +25,7 @@
 
 (define_expand "mem_thread_fence"
   [(match_operand:SI 0 "const_int_operand")]
-  "TARGET_V8 || TARGET_V9"
+  ""
 {
   enum memmodel model = (enum memmodel) INTVAL (operands[0]);
   sparc_emit_membar_for_model (model, 3, 3);
@@ -36,7 +36,7 @@
   [(set (match_dup 1)
 	(unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
 		    UNSPEC_MEMBAR))]
-  "TARGET_V8 || TARGET_V9"
+  ""
 {
   operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
   MEM_VOLATILE_P (operands[1]) = 1;
@@ -49,7 +49,7 @@
 ;; ignore all such barriers on Sparc V7.
 (define_insn "*membar_empty"
   [(set (match_operand:BLK 0 "" "")
-	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
+	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_operand")]
 		    UNSPEC_MEMBAR))]
   ""
   ""
@@ -72,11 +72,11 @@
   "stb\t%%g0, [%%sp-1]"
   [(set_attr "type" "store")])
 
-;; For V8, LDSTUB has the effect of membar #StoreLoad.
+;; For V7/V8, LDSTUB has the effect of membar #StoreLoad.
 (define_insn "*membar_storeload"
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
-  "TARGET_V8 && !TARGET_LEON3"
+  "!TARGET_V9 && !TARGET_LEON3"
   "ldstub\t[%%sp-1], %%g0"
   [(set_attr "type" "multi")])
 
@@ -262,7 +262,7 @@
    (match_operand:SI 1 "memory_operand" "")
    (match_operand:SI 2 "register_operand" "")
    (match_operand:SI 3 "const_int_operand" "")]
-  "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
+  "!sparc_fix_ut699"
 {
   enum memmodel model = (enum memmodel) INTVAL (operands[3]);
 
@@ -278,7 +278,7 @@
 			    UNSPECV_SWAP))
    (set (match_dup 1)
 	(match_operand:SI 2 "register_operand" "0"))]
-  "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
+  "!sparc_fix_ut699"
 {
   if (sparc_fix_gr712rc)
     return ".align\t16\n\tswap\t%1, %0";