Re: port-i386/52266: Double fault early in boot with AMD Am5x86 CPU

[Kimihiro Nonaka <nonakap%gmail.com@localhost>]

2017-07-12 7:45 GMT+09:00 John D. Baker <jdbaker%mylinuxisp.com@localhost>:

>  > Looking at the reports so far and the meaning of each of the various
>  > CPUID_* bits, it looks like:
>  >
>  >   AMD Am5x86 (Elan SC520):  No MSR, No APIC
>  >   NS Geode:  MSR, No APIC, rdmsr_safe() works
>  >   TM Crusoe:  MSR, No APIC, rdmsr_safe() fails
>  >
>  > Are there any CPUs which implement APIC w/o MSR?
>
>  Thinking about it more, if the CPU doesn't implement APIC, why bother
>  reading MSR at all?  As such, Andreas' change to the patch would also
>  satisfy all the cases above and is simpler.

I agree.

Updated the patch.

diff --git a/sys/arch/x86/x86/lapic.c b/sys/arch/x86/x86/lapic.c
index 415bb65b4e5..e3423d8ce07 100644
--- a/sys/arch/x86/x86/lapic.c
+++ b/sys/arch/x86/x86/lapic.c
@@ -237,7 +237,8 @@ lapic_is_x2apic(void)
 {
     uint64_t msr;

-    if (rdmsr_safe(MSR_APICBASE, &msr) == EFAULT)
+    if (!ISSET(cpu_feature[0], CPUID_APIC) ||
+        rdmsr_safe(MSR_APICBASE, &msr) == EFAULT)
         return false;
     return (msr & (APICBASE_EN | APICBASE_EXTD)) ==
         (APICBASE_EN | APICBASE_EXTD);

Regards,
-- 
Kimihiro Nonaka