Re: port-i386/52266: Double fault early in boot with AMD Am5x86 CPU

["John D. Baker" <jdbaker%mylinuxisp.com@localhost>]

The following reply was made to PR port-i386/52266; it has been noted by GNATS.

From: "John D. Baker" <jdbaker%mylinuxisp.com@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: 
Subject: Re: port-i386/52266: Double fault early in boot with AMD Am5x86 CPU
Date: Tue, 11 Jul 2017 17:40:17 -0500 (CDT)

 On Tue, 11 Jul 2017, John D. Baker wrote:
 
 > Looking at the reports so far and the meaning of each of the various
 > CPUID_* bits, it looks like:
 > 
 >   AMD Am5x86 (Elan SC520):  No MSR, No APIC
 >   NS Geode:  MSR, No APIC, rdmsr_safe() works
 >   TM Crusoe:  MSR, No APIC, rdmsr_safe() fails
 > 
 > Are there any CPUs which implement APIC w/o MSR?
 
 Thinking about it more, if the CPU doesn't implement APIC, why bother
 reading MSR at all?  As such, Andreas' change to the patch would also
 satisfy all the cases above and is simpler.
 
 Since the x2apic code hinges on successfully reading MSR to obtain
 MSR_APICBASE, if there's no APIC of which to obtain the base, return
 false.
 
 Or is there some subtlty I'm missing?
 
 -- 
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