[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
Re: Revamping optimised in_cksum/in4_cksum/in6_cksum support
>>> __builtin_prefetch(data + 32);
>> __builtin_prefetch is not supposed to generate traps. If you can
>> actually trigger that, it is a GCC bug.
> At least MIPS and PowerPC will generate "pref" and "dcbt"
> instructions respectively that point to potentially invalid addresses
> with the code as it currently is.
And they can trap? Then surely that's just a bug in the MIPS/PPC
configuration for gcc, no?
> I had a look at the gcc description of __builtin_prefetch() and I'm
> curious as to how "Data prefetch does not generate faults if ADDR is
> invalid" can be guaranteed if it just blindly issues the raw
> cache/prefetch instructions with the addresses you pass it when those
> instructions can fault on at least some CPUs of both the
> architectures I've looked at so far...
Just means the configurations for those CPUs are broken, I'd say.
Sounds to me as though someone implemented prefetching on those CPUs
without reading the specs closely enough (whether the gcc specs or the
CPU specs, I'm in no position to say).
/~\ The ASCII der Mouse
\ / Ribbon Campaign
X Against HTML mouse%rodents.montreal.qc.ca@localhost
/ \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
Main Index |
Thread Index |