tech-kern archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: 4.x -> 5.x locking?

> However, since we aren't talking about non-cache-coherent
> architectures (which require even more manual manipulation) it's only
> about access reordering in the memory hierarchy.

I'm not totally clear on what cache coherency is.  Based on these
remarks, I'm going to guess that a cache-coherent architecture is one
on which, as far as the model visible to the programmer (including
kernel programmer) goes, it is not possible to have conflicting data in
two CPUs' caches: either different CPUs don't have distinct caches, or
there is automatic cache update and/or invalidation in hardware (at
least optionally, and if it's optional then NetBSD runs the hardware in
that mode).

Correct?  If so, that completely annuls the hairiest of my worries.

/~\ The ASCII                             Mouse
\ / Ribbon Campaign
 X  Against HTML      
/ \ Email!           7D C8 61 52 5D E7 2D 39  4E F1 31 3E E8 B3 27 4B

Home | Main Index | Thread Index | Old Index