Re: TLB tiredown by ASID bump

[Eduardo Horvath <eeh%NetBSD.org@localhost>]

On Fri, 7 Jan 2011, Toru Nishimura wrote:

> Eduardo Horvath points an abstruction issue;
> 
> > I think exposing this implementation detail breaks the abstraction layer
> > provided by pmap(9) and thus is a bad thing.  
> 
> True, but it's the matter of pmap(9) specication. TLB is a sort of cache
> and NetBSD intentionally omits to define cache manipuating primitives
> since cache design varies radically among CPU implementations and
> it would make little sense to define "universal cache primitives" good
> enough across varying cache designs.  ASID management falls into
> the same category.and pmap(9) should stay away.

What?  No.  The existance of ASIDs along with the hardware implementation 
is fundamentally a proprty of the MMU design.  Exposing this information 
outside of the MD code base (pmap(9)) breaks encapsulation.

What exactly do you expect to achieve by forcing all ports to add some 
ASID manipulation hook?  Adding some common code to manipulate ASIDS that 
is good for one hardware implementation but lousy for others?  

The whole reason to hide hardware differences behind abstractions is to 
allow for efficient implementation of machine specific functionality.

If you want to provide some generic routines that specific pmap(9) 
implementations can call into fine, but adding some generic hook in all 
the AST code does not look like a good exercise in code encapsulation to 
me.  Or am I missing something?

Eduardo