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Re: TLB tiredown by ASID bump
Eduardo Horvath points an abstruction issue;
I think exposing this implementation detail breaks the abstraction layer
provided by pmap(9) and thus is a bad thing.
True, but it's the matter of pmap(9) specication. TLB is a sort of cache
and NetBSD intentionally omits to define cache manipuating primitives
since cache design varies radically among CPU implementations and
it would make little sense to define "universal cache primitives" good
enough across varying cache designs. ASID management falls into
the same category.and pmap(9) should stay away.
Toru Nishimura / ALKYL Technology
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