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CVS commit: src/sys/arch/riscv/starfive



Module Name:    src
Committed By:   skrll
Date:           Wed Sep 18 10:33:36 UTC 2024

Modified Files:
        src/sys/arch/riscv/starfive: jh7110_clkc.c

Log Message:
Match "Image-Signal-Process" clock controller and only aprint_debug the
state of "System" and "Always-On" clocks.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/starfive/jh7110_clkc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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