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Re: I2O on sparc64 (Was: Re: mlx on sparc?)

Am 17.09.2008 um 00:25 schrieb Michael L. Hitch:

On Tue, 16 Sep 2008, Jan-Hinrich Fessel wrote:

indeed, doesn't look too bad:
Distributed Processing Technology Memory Controller (miscellaneous memory, revision 0x02) at pci2 dev 3 function 0 not configured
iop0 at pci2 dev 4 function 0: I2O adapter <DPT PM3755U2B>
iop0: orgid=0x001b version=1
iop0: type want have cbase
iop0: mem  0000 0000 00000000
iop0: i/o  0000 0000 00000000
iop0: interrupting at ivec 1c
iop0: queue depths: inbound 256/256, outbound 256/256

mem and i/o - is that correct?

I don't know; I didn't have the debugging turned on in my driver, but it looks like it's the same thing as returned by iopctl showstatus, and
on my alpha, it looks like they are the same.

Looking closer, it seems quite logical, since the memory controller of that board is not recognized by the kernel, thus leaving it in uninitialized state. Which might make the board think there is no memory present. Does anyone have docs about this memory controller? Google didn't find any usable results for me - and dpt.com isn't reachable from my provider's network.


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