Re: I2O on sparc64 (Was: Re: mlx on sparc?)

["Michael L. Hitch" <mhitch%lightning.msu.montana.edu@localhost>]

On Tue, 16 Sep 2008, Jan-Hinrich Fessel wrote:

> indeed, doesn't look too bad:
> Distributed Processing Technology Memory Controller (miscellaneous memory, 
> revision 0x02) at pci2 dev 3 function 0 not configured
> iop0 at pci2 dev 4 function 0: I2O adapter <DPT PM3755U2B>
> iop0: orgid=0x001b version=1
> iop0: type want have cbase
> iop0: mem  0000 0000 00000000
> iop0: i/o  0000 0000 00000000
> iop0: interrupting at ivec 1c
> iop0: queue depths: inbound 256/256, outbound 256/256
>
> mem and i/o - is that correct?

  I don't know;  I didn't have the debugging turned on in my driver, but
it looks like it's the same thing as returned by iopctl showstatus, and
on my alpha, it looks like they are the same.

> # iopctl showstatus
> organization id          27
> iop id                   4095
> host unit id             0
> segment number           0
> i2o version              1
> iop state                8
> messenger type           0
> inbound frame sz         8388608
                           ^^^^^^^
                           This appears to be the only difference I see.

> init code                128
> max inbound queue depth  256
> inbound queue depth      256
> max outbound queue depth 256
> product id string        <DPT PM3755U2B>
> expected lct size        3693
> iop capabilities         0x00000000
> desired priv mem sz      0x00000000
> current priv mem sz      0x00000000
> current priv mem base    0x00000000
> desired priv io sz       0x00000000
> current priv io sz       0x00000000
> current priv io base     0x00000000


es45# iopctl showstatus
organization id          27
iop id                   4095
host unit id             0
segment number           0
i2o version              1
iop state                8
messenger type           0
inbound frame sz         128
init code                128
max inbound queue depth  256
inbound queue depth      256
max outbound queue depth 256
product id string        <DPT PM3755U2B>
expected lct size        3693
iop capabilities         0x00000000
desired priv mem sz      0x00000000
current priv mem sz      0x00000000
current priv mem base    0x00000000
desired priv io sz       0x00000000
current priv io sz       0x00000000
current priv io base     0x00000000


--
Michael L. Hitch                        mhitch%montana.edu@localhost
Computer Consultant
Information Technology Center
Montana State University        Bozeman, MT     USA