Re: Berkeley db 4.8 and newer, and sparc

[Eduardo Horvath <eeh%NetBSD.org@localhost>]

On Thu, 28 Oct 2010, Hauke Fath wrote:

> o What is the equivalent of the above assembler code for SPARC v7?
> o How does that equivalent work with v8 and v9 (sparc32 mode) cpus? With MP
> machines?
> o Or do we have to build specifically for the target cpu?
> o Do we have any #defines besides __sparc__ and __sparc64__ to tell us
> which cpu gcc creates code for?
> o Is there a completely different way that I cannot see?

V7 does not have any memory ordering insructions.

V8 added STBAR and FLUSH.  FLUSH is only required for self-modifying code.  
STBAR decodes to a noop on v7 machines, so they can be added to code 
wihout affecting v7 machines.

On SPARC V9 machines we run 32-bit processes with the TSO memory model so 
no barrier instructions are needed.  32-bit binaries do not use v9 
instructions.

64-bit processes use whatever memory model is encoded in the ELF header or 
RMO which means we do need all the fancy memory barrier instrucions.

You should be able to use __arch64__ to compile in the memory barriers 
only for 64-bit code.

If you're running V8 in PSO mode the LDSTUB does not need memory barriers.  
An atomic unlock using STB does however:

unlock:
        stbar
        stub    %g0, [lock]

Eduardo