Berkeley db 4.8 and newer, and sparc

[Hauke Fath <hf%spg.tu-darmstadt.de@localhost>]

All,

the Berkeley db versions >= 4.8 do not build on sparc - see PR pkg/43444.
db v4.8 did away with fcntl locking , see
<http://forums.oracle.com/forums/thread.jspa?messageID=8398331>. Since
NetBSD lacks pthread_rwlock_*() support, we cannot configure
--with-mutex=POSIX/pthreads. And the db code ships with SPARC v9 exclusive
mutex assembler code.

Autoconf tries to explore (db-4.8.30/dist/configure) locking capabilities
with the SPARC v9 only


        #if defined(__sparc__) && defined(__GNUC__)
                asm volatile ("membar =
 #StoreStore|#StoreLoad|#LoadStore");
                exit(0);
        #else
                FAIL TO COMPILE/LINK
        #endif


and the sparc mutex code in db-4.8.30/dbinc/mutex_int.h has:

<snip>
#ifdef HAVE_MUTEX_SPARC_GCC_ASSEMBLY
typedef unsigned char tsl_t;

#define MUTEX_ALIGN     8

#ifdef LOAD_ACTUAL_MUTEX_CODE
/*
  * The ldstub instruction takes the location specified by its first argument
  * (a register containing a memory address) and loads its contents into its
  * second argument (a register) and atomically sets the contents the location
  * specified by its first argument to a byte of 1s.  (The value in the second
  * argument is never read, but only overwritten.)
  *
  * Hybrid mutexes require membar #StoreLoad and #LoadStore ordering on multi-
  * processor v9 systems.
  *
  * gcc/sparc: 0 is clear, 1 is set.
  */
#define MUTEX_SET(tsl) ({                                               \
        register tsl_t *__l = (tsl);                                    \
        register tsl_t __r;                                             \
        __asm__ volatile                                                \
            ("ldstub [%1],%0; stbar"                                    \
            : "=r"( __r) : "r" (__l));                                  \
        !__r;                                                           \
})

#define MUTEX_UNSET(tsl)        (*(tsl) = 0, MUTEX_MEMBAR(tsl))
#define MUTEX_INIT(tsl)         (MUTEX_UNSET(tsl), 0)
#define MUTEX_MEMBAR(x) \
        ({ __asm__ volatile ("membar #StoreStore|#StoreLoad|#LoadStore"); })
#define MEMBAR_ENTER() \
        ({ __asm__ volatile ("membar #StoreStore|#StoreLoad"); })
#define MEMBAR_EXIT() \
        ({ __asm__ volatile ("membar #StoreStore|#LoadStore"); })
#endif
#endif
</snip>

Now, unfortunately, I couldn't SPARC assembler code my way out of the
proverbial paper bag. My questions:

o What is the equivalent of the above assembler code for SPARC v7?
o How does that equivalent work with v8 and v9 (sparc32 mode) cpus? With MP
machines?
o Or do we have to build specifically for the target cpu?
o Do we have any #defines besides __sparc__ and __sparc64__ to tell us
which cpu gcc creates code for?
o Is there a completely different way that I cannot see?

Thanks for reading this far,

        hauke


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