Re: PowerPC TODO list

[Jochen Roth <jochen%panix.com@localhost>]

rjs%fdy2.demon.co.uk@localhost wrote:
> root%garbled.net@localhost wrote:
> > On 25-Apr-2008 rjs%fdy2.demon.co.uk@localhost wrote:
> > > The same happens on ibmnws which uses the same chip.
> > >
> > > Linux on the ibmnws pokes some magic numbers into the DMA controller.
> > Which driver is that, or what file is that located in?  I'm having troubl=
> > e
> > finding that in the linux source tree mess.
>
> In arch/ppc/platforms/prep_pci.c from the patched 2.4.21-ns1000 tree.
>
> I have run kernels built from this tree and sound does work.

Apologies for the abundant source code comments...

Basically, the NWS firmware does not initialize the DMA controllers in 
the 82378 ISA bridge the way an x86 PC BIOS would do.

From memory, important ISA DMA controller weirdness: AT and later used 
two DMA controller chips. DMA 0-3 is 8 bits wide, and DMA5-7 is 16 bits. 
The 8 bit controller chains into the 16 bit controller where DMA4 would 
have been. The 16 bit chip was wired up with address bits shifted one 
position, i.e. LSB of address is always 0. I think this was done to 
effectively double the maximum DMA transfer size for the 16 bit 
channels. This means that a) the chip register offsets are twice what 
they are for the 8 bit chip, and b) the 16 bit chip gets set up for 8 
bit mode operation.

I added some comments below.

> #ifdef CONFIG_NS1000
> static void __init isa_init_dma(void)
> {
>         printk("Initializing ISA DMA controller\n");
>
>         outb(0xff, 0x0d);       /* dma1 master clear */
>         outb(0xff, 0xda);       /* dma2 master clear */
        /* DMA channel mode register DMA0-3: Single Mode */
>         outb(0x40, 0x0b); 
>         outb(0x41, 0x0b); 
>         outb(0x42, 0x0b);
>         outb(0x43, 0x0b); 
        /* DMA channel mode register DMA4: Cascade Mode */
>         outb(0xc0, 0xd6); 
        /* DMA channel mode register DMA5-7: Single Mode */
>         outb(0x41, 0xd6);
>         outb(0x42, 0xd6);
>         outb(0x43, 0xd6);
        /* Clear the mask bits for DMA4-7 */
>         outb(0, 0xd4);
        /* Clear command registers */
>         outb(0x10, 0x08);
>         outb(0x10, 0xd0);
        /* Extended mode registers: 8bit, count bytes, fast mode */
>         outb(0x30, 0x40b);
>         outb(0x31, 0x40b);
>         outb(0x32, 0x40b);
>         outb(0x33, 0x40b);
>         outb(0x31, 0x4d6);
>         outb(0x32, 0x4d6);
>         outb(0x33, 0x4d6);
>
>         request_region(0x000, 0x10, "dma1");
>         request_region(0x0c0, 0x20, "dma2");
>         request_region(0x080, 0x10, "dma low pages");
>         request_region(0x480, 0x10, "dma high pages");
> }
> #endif