Deciphering GPIO on Raspberry Pi B+

[Jason Thorpe <thorpej%me.com@localhost>]

NetBSD reports the following:

fdt0 at armfdt0: Raspberry Pi Model B Plus Rev 1.2
.
.
.
bcmgpio0 at fdt1: GPIO controller
gpio0 at bcmgpio0: 32 pins
gpio1 at bcmgpio0: 22 pins

The actual device tree looks like this:

00000af0:     /gpio@7e200000
00000d78:       /dpi_gpio0
00000e18:       /emmc_gpio22
00000e60:       /emmc_gpio34
00000ecc:       /emmc_gpio48
00000f34:       /gpclk0_gpio4
00000f6c:       /gpclk1_gpio5
00000fa4:       /gpclk1_gpio42
00000fdc:       /gpclk1_gpio44
00001014:       /gpclk2_gpio6
0000104c:       /gpclk2_gpio43
00001084:       /i2c0_gpio0
000010dc:       /i2c0_gpio28
00001114:       /i2c0_gpio44
0000114c:       /i2c1_gpio2
000011a4:       /i2c1_gpio44
000011dc:       /i2c_slave_gpio18
00001224:       /jtag_gpio4
00001268:       /jtag_gpio22
000012b0:       /pcm_gpio18
000012f0:       /pcm_gpio28
00001330:       /pwm0_gpio12
00001364:       /pwm0_gpio18
00001398:       /pwm0_gpio40
000013ec:       /pwm1_gpio13
00001420:       /pwm1_gpio19
00001454:       /pwm1_gpio41
00001488:       /pwm1_gpio45
000014dc:       /sdhost_gpio48
00001548:       /spi0_gpio7
0000158c:       /spi0_gpio35
000015d0:       /spi1_gpio16
00001618:       /spi2_gpio40
00001660:       /uart0_gpio14
000016bc:       /uart0_ctsrts_gpio16
000016fc:       /uart0_ctsrts_gpio30
0000173c:       /uart0_gpio32
00001778:       /uart0_gpio36
000017b4:       /uart0_ctsrts_gpio38
000017f4:       /uart1_gpio14
00001830:       /uart1_ctsrts_gpio16
00001870:       /uart1_gpio32
000018ac:       /uart1_ctsrts_gpio30
000018ec:       /uart1_gpio40
00001928:       /uart1_ctsrts_gpio42
00001968:       /gpioout
000019b8:       /alt0
00001a20:       /i2s_alt0

Then I see this choice little bit of code:

        gba.gba_gc = &sc->sc_gpio_gc;
        for (pin = 0; pin < BCMGPIO_MAXPINS;) {
                const int npins = MIN(BCMGPIO_MAXPINS - pin, 32);
                gba.gba_pins = &sc->sc_gpio_pins[pin];
                gba.gba_npins = npins;
                config_found_ia(self, "gpiobus", &gba, gpiobus_print);
                pin += npins;
        }

So, can I assume that the only reason this is broken up into 2 separate “gpio” instances is because the GPIO subsystem can’t handle more than 32 pins on a single controller?

And what’s the best way to figure out which GPIO pins are available for application use and not consumed by other system functions?

-- thorpej