Re: Deciphering GPIO on Raspberry Pi B+

[Hal Murray <hmurray%megapathdsl.net@localhost>]

I haven't worked with this particular chip, but I have worked with several 
other ARM chips.

thorpej%me.com@localhost said:
> So, can I assume that the only reason this is broken up into 2 separate
> â??gpioâ?? instances is because the GPIO subsystem canâ??t handle more than 32
> pins on a single controller? 

I'd expect the hardware to work in blocks of 32 bits.  If they are in the 
same block, you can turn on/off several GPIO bits on the same clock cycle.

My mental picture of the silicon is a bunch of registers and perpendicular to 
that is the logic for each GPIO bit.


> And whatâ??s the best way to figure out which GPIO pins are available for
> application use and not consumed by other system functions?

The basic idea is that GPIO gets all the leftovers.  If a pin isn't used for 
something else, you can use it for GPIO.

Interesting functions are often connected to more than one pin so you can 
still get at it if N-1 pins are used for something else.  So when you are 
setting things up, you may have to decide which pins a function is going to 
use.  In addition, some uses are optional.  A simple example is the modem 
control signals for a UART.  Sometimes you don't pay attention to them.  
Sometimes you need them.

GPIO can probably read the data on a pin even if it is being used for 
something else and/or even if it isn't connected to an external pin.  There 
is probably a register that drives an output multiplexor that selects what 
goes to the pin driver and another register than enables the driver.  It's 
probably part of the GPIO logic.  There may be some pins that have 3 uses, 
but only 2 of them are output.  That's GPIO and one other.

Here is your table sorted by GPIO pin number.

Note that pwm0 is shared with gpio12, gpio18 and gpio40.

00000d78:       /dpi_gpio0
00001084:       /i2c0_gpio0
0000114c:       /i2c1_gpio2
00000f34:       /gpclk0_gpio4
00001224:       /jtag_gpio4
00000f6c:       /gpclk1_gpio5
00001014:       /gpclk2_gpio6
00001548:       /spi0_gpio7

00001330:       /pwm0_gpio12
000013ec:       /pwm1_gpio13
00001660:       /uart0_gpio14
000017f4:       /uart1_gpio14
000016bc:       /uart0_ctsrts_gpio16
000015d0:       /spi1_gpio16
00001830:       /uart1_ctsrts_gpio16
000011dc:       /i2c_slave_gpio18
000012b0:       /pcm_gpio18
00001364:       /pwm0_gpio18
00001420:       /pwm1_gpio19

00000e18:       /emmc_gpio22
00001268:       /jtag_gpio22
000010dc:       /i2c0_gpio28
000012f0:       /pcm_gpio28

000016fc:       /uart0_ctsrts_gpio30
000018ac:       /uart1_ctsrts_gpio30
0000173c:       /uart0_gpio32
00001870:       /uart1_gpio32
00000e60:       /emmc_gpio34
0000158c:       /spi0_gpio35
00001778:       /uart0_gpio36
000017b4:       /uart0_ctsrts_gpio38

00001398:       /pwm0_gpio40
00001618:       /spi2_gpio40
000018ec:       /uart1_gpio40
00001454:       /pwm1_gpio41
00000fa4:       /gpclk1_gpio42
00001928:       /uart1_ctsrts_gpio42
0000104c:       /gpclk2_gpio43
00000fdc:       /gpclk1_gpio44
00001114:       /i2c0_gpio44
000011a4:       /i2c1_gpio44
00001488:       /pwm1_gpio45
00000ecc:       /emmc_gpio48
000014dc:       /sdhost_gpio48



-- 
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