Port-arm archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
Anybody have MIRABOX working?
With an as-yet-uncommitted patch from Matt Thomas, a MIRABOX kernel
boots as far as asking for root:
Marvell>> tftp 1640000 mirabox.gz.ub
phyaddr= 0
Using egiga0 device
TFTP from server 10.187.0.10; our IP address is 10.187.0.64
Filename 'mirabox.gz.ub'.
Load address: 0x1640000
Loading: #################################################################
#####################################################
done
Bytes transferred = 1719097 (1a3b39 hex)
Marvell>> bootm
## Booting kernel from Legacy Image at 01640000 ...
Image Name: NetBSD/mirabox 7.99.1
Created: 2014-08-24 21:10:13 UTC
Image Type: ARM NetBSD Kernel Image (gzip compressed)
Data Size: 1719033 Bytes = 1.6 MB
Load Address: 01000000
Entry Point: 01000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
## Transferring control to NetBSD stage-2 loader (at address 01000000) ...
[ Kernel symbol table missing! ]
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 7.99.1 (MIRABOX) #3: Sun Aug 24 14:10:09 PDT 2014
riz%cassava.tastylime.net@localhost:/scratch/evbarm7/obj/sys/arch/evbarm/compile/MIRABOX
total memory = 1024 MB
avail memory = 1009 MB
sysctl_createv: sysctl_create(machine_arch) returned 17
kern.module.path=/stand/evbarm/7.99.1/modules
mainbus0 (root)
cpu0 at mainbus0 core 0: 1 GHz Sheeva 88SV581x rev 1 (Marvell V core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB/32B 4-way L1 PIPT Instruction cache
cpu0: 32KB/32B 8-way write-back-locking-C L1 VIPT Data cache
vfp0 at cpu0: VFP3, rounding, exceptions, NaN propagation
mvsoc0 at mainbus0: Marvell MV6710 Rev. A1 Armada 370
mvsoc0: CPU Clock 1000.000 MHz SysClock 1000.000 MHz TClock 200.000 MHz
mvsoctmr0 at mvsoc0 unit 0 offset 0x20300-0x203ff irq 37: Marvell SoC Timer
com0 at mvsoc0 unit 0 offset 0x12000-0x1201f irq 41: ns16550a, working fifo
com0: console
com1 at mvsoc0 unit 1 offset 0x12100-0x1211f irq 42: ns16550a, working fifo
mvsocrtc0 at mvsoc0 unit 0 offset 0x10300-0x10317 irq 50: Marvell SoC
Real Time Clock
gttwsi0 at mvsoc0 unit 0 offset 0x11000-0x110ff irq 31: Marvell TWSI
controller
iic0 at gttwsi0: I2C bus
gttwsi0: unexpected status 0x20: expect 0x18
gttwsi1 at mvsoc0 unit 1 offset 0x11100-0x111ff irq 32: Marvell TWSI
controller
iic1 at gttwsi1: I2C bus
gttwsi1: unexpected status 0xf8: expect 0x18
gtidmac at mvsoc0 unit 0 not configured
ehci0 at mvsoc0 unit 0 offset 0x50000-0x50fff irq 45: Marvell USB 2.0
Interface
usb0 at ehci0: USB revision 2.0
ehci1 at mvsoc0 unit 1 offset 0x51000-0x51fff irq 46: Marvell USB 2.0
Interface
usb1 at ehci1: USB revision 2.0
mvpex0 at mvsoc0 unit 0 offset 0x40000-0x41fff irq 58: Marvell PCI
Express Interface
pci0 at mvpex0
vendor 0x11ab product 0x6710 (miscellaneous memory, revision 0x01) at
pci0 dev 0 function 0 not configured
mvsoc0: mvpex1 clock disabled
mvsata0 at mvsoc0 unit 0 offset 0xa0000-0xa7fff irq 55: Marvell
Serial-ATA Host Controller (SATAHC)
mvsata0: GenIIe, 1hc, 2port/hc
atabus0 at mvsata0 channel 0
atabus1 at mvsata0 channel 1
mvspi0 at mvsoc0 unit 0 offset 0x10600-0x1064f irq 30: Marvell SPI
controller
spi0 at mvspi0: SPI bus
m25p0 at spi0 slave 0: unknown or unsupported device
mvspi1 at mvsoc0 unit 1 offset 0x10600-0x1064f irq 30: Marvell SPI
controller
spi1 at mvspi1: SPI bus
mvsdio0 at mvsoc0 unit 0 offset 0xd4000-0xe3fff irq 54: Marvell Secure
Digital Input/Output Interface
sdmmc0 at mvsdio0
mvgbec0 at mvsoc0 unit 0 offset 0x70000-0x73fff: Marvell Gigabit
Ethernet Controller
mvgbe0 at mvgbec0 port 0 irq 66
mvgbe0: Port Version 0x10
mvgbe0: Ethernet address f0:ad:4e:01:a5:d3
ukphy0 at mvgbe0 phy 0: OUI 0x000ac2, model 0x001d, rev. 1
ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
1000baseT-FDX, auto
mvgbec1 at mvsoc0 unit 1 offset 0x74000-0x77fff: Marvell Gigabit
Ethernet Controller
mvgbe at mvgbec1 port 0 not configured
mvcesa0 at mvsoc0 unit 0 offset 0x9d000-0x9dfff irq 48: Marvell
Cryptographic Engines and Security Accelerator
uhub0 at usb0: Marvell EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub1 at usb1: Marvell EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
"Marvell, 802.11 SDIO ID: 20, " (manufacturer 0x2df, product 0x9118) at
sdmmc0 function 1 not configured
"Marvell, 802.11 SDIO ID: 20, " (manufacturer 0x2df, product 0x9118) at
sdmmc0 function 2 not configured
"Marvell, 802.11 SDIO ID: 20, " (manufacturer 0x2df, product 0x9118) at
sdmmc0 function 3 not configured
uhub2 at uhub0 port 1: vendor 0x1a40 USB 2.0 Hub, class 9/0, rev
2.00/1.11, addr 2
uhub2: single transaction translator
umass0 at uhub2 port 1 configuration 1 interface 0
umass0: Generic USB Storage, rev 2.00/94.51, addr 3
scsibus0 at umass0: 2 targets, 1 lun per target
sd0 at scsibus0 target 0 lun 0: <Generic, STORAGE DEVICE, 9451> disk
removable
sd0: drive offline
umass1 at uhub2 port 2 configuration 1 interface 0
umass1: Generic USB Storage, rev 2.00/94.51, addr 4
scsibus1 at umass1: 2 targets, 1 lun per target
sd1 at scsibus1 target 0 lun 0: <Generic, STORAGE DEVICE, 9451> disk
removable
sd1: drive offline
boot device: <unknown>
root device:
... however, I can't get it to work with sd0, sd1 *or* mvgbe0.:
root device: sd0a
dump device (default sd0b):
file system (default generic):
root on sd0a dumps on sd0b
sd0(umass0:0:0:0): not ready, data = 00 00 00 00 3a 00 00 00 00 00
sd0(umass0:0:0:0): not ready, data = 00 00 00 00 3a 00 00 00 00 00
vfs_mountroot: can't open root device
cannot mount root, error = 19
root device (default sd0a): sd1a
dump device (default sd1b):
file system (default generic):
root on sd1a dumps on sd1b
sd1(umass1:0:0:0): not ready, data = 00 00 00 00 3a 00 00 00 00 00
vfs_mountroot: can't open root device
cannot mount root, error = 19
root device (default sd1a):
Did anyone ever have devices on the mirabox working? If so, what's a
known-working tree?
Here's the patch I need to get the kernel booting at all (from Matt Thomas):
Index: sys/arch/arm/arm/cpufunc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.150
diff -u -r1.150 cpufunc.c
--- sys/arch/arm/arm/cpufunc.c 31 Jul 2014 07:14:42 -0000 1.150
+++ sys/arch/arm/arm/cpufunc.c 25 Aug 2014 18:39:20 -0000
@@ -2151,7 +2151,7 @@
cputype == CPU_ID_ARM_88SV581X_V6 ||
cputype == CPU_ID_ARM_88SV581X_V7) &&
(armreg_pfr0_read() & ARM_PFR0_THUMBEE_MASK)) {
- cpufuncs = pj4bv7_cpufuncs;
+ cpufuncs = armv7_cpufuncs;
#if defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
cpu_armv7_p = true;
#endif
Home |
Main Index |
Thread Index |
Old Index