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Re: earmhf issues on Beaglebone Black

On Jul 25, 2014, at 7:57 AM, Nick Hudson <skrll%netbsd.org@localhost> wrote:

> On 07/25/14 15:43, Manuel Bouyer wrote:
>> The RPI CPU has a VIVT L1 data cache, which could explain the
>> behavior difference (pmap_zero_page_generic() will behaves differently).
>> But I'm still surprised that it didn't cause more problems.
> RPI L1 is VIPT.
> cpu0 at mainbus0 core 0: 700 MHz ARM1176JZ-S r0p7 (ARM11J V6ZK core)
> cpu0: DC enabled IC enabled WB enabled LABT
> cpu0: 16KB/32B 4-way L1 VIPT Instruction cache
> cpu0: 16KB/32B 4-way write-back-locking-C L1 VIPT Data cache

Actually, the A8 L1-D is PIPT, only the L1-I is VIPT

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