Re: Booting NetBSD/evbarm on QEMU (IntegratorCP)

[Sergio López <slp%sinrega.org@localhost>]

2013/2/8 Jeff Rizzo <riz%boogers.sf.ca.us@localhost>:
> Playing around a bit more, I suspect there's some timer issues;  for
> example, pinging another host results in a several-second-per-packet delay,
> though the RTTs look reasonable and short.  Also, the RTC loses about 30m
> per hour.
>

Thanks for the QA! :-)

I've produced a new patch:

http://blogs.nologin.es/slopez/uploads/integrator-cp-2013-02-08.diff

and a new kernel image:

http://blogs.nologin.es/slopez/uploads/netbsd-2013-02-08.gz.ub

with the following changes:

 - Use the name INTEGRATOR_CP instead of INTEGRATOR_QEMU.
 - Compile by default for ARM9/10/11.
 - Include support for bpfilter.
 - Rename most magic number references.
 - Use proper timing values for IntegratorCP (1Mhz instead of 24Mhz).
This removes the kludge in ifpga_clock.c:cpu_initclocks, and should
fix the clock going backwards issue.

Also, I'd like to mention I've pinpointed the broken VFP support to
these commits (it worked before):

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/arm/vfp/vfp_init.c.diff?r1=1.17&r2=1.18&only_with_tag=MAIN
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/arm/vfp/vfp_init.c.diff?r1=1.18&r2=1.19&only_with_tag=MAIN

With the first one, compilation fails just as it says in the commit
log, and the latter makes the kernel panic like this:

<---->
cpu0 at mainbus0 core 0: ARM1136J-S r1p3 (ARM11J V6J core)
cpu0: DC enabled IC enabled WB disabled EABT
cpu0: 4KB/32B 4-way L1 Instruction cache
cpu0: 64KB/32B 4-way write-through L1 Data cache
Undefined instruction in kernel
Stopped in pid 0.1 (system) at  netbsd:vfp_attach+0x124:        mrc
 p10, 7, r
1, c7, c0, 0
db>
<---->

I haven't took much time to look into this, so I'm not sure if this is
a problem with QEMU, binutils, or that piece of code.

Sergio.