Re: ARM L2 cache support?

["Jonathan A. Kollasch" <jakllsch%kollasch.net@localhost>]

On Fri, Aug 27, 2010 at 02:48:11PM +0100, rjs%fdy2.demon.co.uk@localhost wrote:
> 
> Rafal Jaworowski wrote:
> >On 2010-08-27, at 07:27, KIYOHARA Takashi wrote:
> >
> >> What status to support for ARM L2 cache?
> >> CPU core new of recent has L2 cache.  For instance, it is Cortex and
> >> Marvell Sheeva.
> >> My neither Sheevaplug nor Overo seem to work if L2 is not disabled now.
> >> 
> >> Do you know the person who is doing the activity of the L2 cache support?
> >
> >If this helps you can have a look at what we have implemented in
> >FreeBSD for Marvell L2 cache module in Kirkwood SoC:
> >http://fxr.watson.org/fxr/source/arm/arm/cpufunc_asm_sheeva.S
> 
> It doesn't really help, NetBSD doesn't have the extra l2cache_* functions
> that are in FreeBSD.
> 
> OTOH, there isn't much point in adding calls to L2 support functions
> in the VM system if manufacturers are not going to provide documentation.

In principle I'd agree.  But the code is there and looks to be
straightforward to understand for someone who understands our
ARM pmap or whatever it's called that does whatever this is doing.

Also, how big is the performance hit of no L2 cache?

        Jonathan Kollasch