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Re: ARM L2 cache support?

On 2010-08-27, at 07:27, KIYOHARA Takashi wrote:

> What status to support for ARM L2 cache?
> CPU core new of recent has L2 cache.  For instance, it is Cortex and
> Marvell Sheeva.
> My neither Sheevaplug nor Overo seem to work if L2 is not disabled now.
> Do you know the person who is doing the activity of the L2 cache support?

If this helps you can have a look at what we have implemented in FreeBSD for 
Marvell L2 cache module in Kirkwood SoC:


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