yosys - Import github.com/cliffordwolf/yosys

[Sevan Janiyan <venture37%geeklan.co.uk@localhost>]

Module Name:	pkgsrc-wip
Committed By:	Sevan Janiyan <venture37%geeklan.co.uk@localhost>
Pushed By:	sevan
Date:		Tue Feb 14 06:32:16 2017 +0000
Changeset:	a7471dfd1080a485432978ec5d521f7b618c53d4

Added Files:
	yosys/DESCR
	yosys/Makefile
	yosys/PLIST
	yosys/distinfo

Log Message:
yosys - Import github.com/cliffordwolf/yosys

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=a7471dfd1080a485432978ec5d521f7b618c53d4

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 yosys/DESCR    |  2 ++
 yosys/Makefile | 37 +++++++++++++++++++++++++++++++++++++
 yosys/PLIST    |  1 +
 yosys/distinfo |  6 ++++++
 4 files changed, 46 insertions(+)

diffs:
diff --git a/yosys/DESCR b/yosys/DESCR
new file mode 100644
index 0000000000..734d4f6748
--- /dev/null
+++ b/yosys/DESCR
@@ -0,0 +1,2 @@
+Yosys currently has extensive Verilog-2005 support and provides a basic set of
+synthesis algorithms for various application domains.
diff --git a/yosys/Makefile b/yosys/Makefile
new file mode 100644
index 0000000000..c306474351
--- /dev/null
+++ b/yosys/Makefile
@@ -0,0 +1,37 @@
+# $NetBSD$
+
+DISTNAME=	yosys-a44cc7a
+CATEGORIES=	devel
+MASTER_SITES=	${MASTER_SITE_GITHUB:=cliffordwolf/}
+GITHUB_TAG= 	69468d5a16f87616af9c7f084f6ff247f3513050
+
+MAINTAINER=	pkgsrc-users%NetBSD.org@localhost
+HOMEPAGE=	https://github.com/cliffordwolf/
+COMMENT=	Yosys is a framework for Verilog RTL synthesis
+LICENSE=	isc
+
+USE_LANGUAGES+=	c c++
+USE_TOOLS+=	gmake pkg-config bison
+#PYTHON_VERSIONS_ACCEPTED= 36 35 34
+PYTHON_VERSIONS_INCOMPATIBLE= 	27
+PKGCONFIG_CONFIG= 	${PKG_CONFIG:Q}
+
+WRKSRC= 		${WRKDIR}/yosys-${GITHUB_TAG}
+
+SUBST_CLASSES+= 	python
+SUBST_MESSAGE.python= 	Fixing non-shellbang references to python3.
+SUBST_STAGE.python= 	pre-configure
+SUBST_SED.python= 	-e 's,python3,${PYTHONBIN},g'
+SUBST_FILES.python= 	techlibs/common/cellhelp.py \
+		techlibs/common/Makefile.inc techlibs/ice40/brams_init.py \
+		techlibs/ice40/Makefile.inc techlibs/xilinx/brams_init.py \
+		techlibs/xilinx/Makefile.inc tests/bram/generate.py tests/bram/run-test.sh \
+		tests/fsm/generate.py tests/fsm/run-test.sh tests/realmath/generate.py \
+		tests/realmath/run-test.sh tests/share/generate.py tests/share/run-test.sh \
+		tests/tools/txt2tikztiming.py
+
+.include "../../mk/readline.buildlink3.mk"
+.include "../../devel/readline/buildlink3.mk"
+.include "../../lang/python/application.mk"
+.include "../../devel/libffi/buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/yosys/PLIST b/yosys/PLIST
new file mode 100644
index 0000000000..48d96a5493
--- /dev/null
+++ b/yosys/PLIST
@@ -0,0 +1 @@
+@comment $NetBSD$
diff --git a/yosys/distinfo b/yosys/distinfo
new file mode 100644
index 0000000000..3971ed0148
--- /dev/null
+++ b/yosys/distinfo
@@ -0,0 +1,6 @@
+$NetBSD$
+
+SHA1 (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = 3828b254ddfbbcbb4e683bdf90fb2ea95c1c318d
+RMD160 (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = d1323bbd2795c21bc8cfb369371f5f482906c896
+SHA512 (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = 10f298a99dd64635f49621f925bfee8f35545e449b0e4fb5dc76f3fc62adcf30862345aeaf4e1e7ef4b0499c8c3240928608b2b33d6c900ca89b04e6f536bc13
+Size (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = 981426 bytes