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coreclr-git: Fix build with LLVM-3.9



Module Name:	pkgsrc-wip
Committed By:	Kamil Rytarowski <n54%gmx.com@localhost>
Pushed By:	kamil
Date:		Tue May 3 13:36:06 2016 +0200
Changeset:	89d187d173222c0b7167f6e33c11009f1f858640

Modified Files:
	coreclr-git/distinfo
Added Files:
	coreclr-git/patches/patch-src_vm_amd64_jithelpers__fast.S
	coreclr-git/patches/patch-src_vm_amd64_jithelpers__fastwritebarriers.S
	coreclr-git/patches/patch-src_vm_amd64_jithelpers__slow.S
	coreclr-git/patches/patch-tests_src_Interop_StructMarshalling_PInvoke_MarshalStructAsParamDLL.h

Log Message:
coreclr-git: Fix build with LLVM-3.9

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=89d187d173222c0b7167f6e33c11009f1f858640

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 coreclr-git/distinfo                               |  4 ++
 .../patches/patch-src_vm_amd64_jithelpers__fast.S  | 22 ++++++++
 ...ch-src_vm_amd64_jithelpers__fastwritebarriers.S | 58 ++++++++++++++++++++++
 .../patches/patch-src_vm_amd64_jithelpers__slow.S  | 18 +++++++
 ...ctMarshalling_PInvoke_MarshalStructAsParamDLL.h | 20 ++++++++
 5 files changed, 122 insertions(+)

diffs:
diff --git a/coreclr-git/distinfo b/coreclr-git/distinfo
index afc7651..0028617 100644
--- a/coreclr-git/distinfo
+++ b/coreclr-git/distinfo
@@ -1,2 +1,6 @@
 $NetBSD$
 
+SHA1 (patch-src_vm_amd64_jithelpers__fast.S) = 8fdb350dc1950c38a166f38a2f859632c35d79f7
+SHA1 (patch-src_vm_amd64_jithelpers__fastwritebarriers.S) = 1d69d2504344742c17f4958c2089d3c3734bbd38
+SHA1 (patch-src_vm_amd64_jithelpers__slow.S) = 74c507a248de6d7f2b075d14be9147095845c00d
+SHA1 (patch-tests_src_Interop_StructMarshalling_PInvoke_MarshalStructAsParamDLL.h) = 21df71b15e3352442eba340cd38ec6a691939229
diff --git a/coreclr-git/patches/patch-src_vm_amd64_jithelpers__fast.S b/coreclr-git/patches/patch-src_vm_amd64_jithelpers__fast.S
new file mode 100644
index 0000000..3990383
--- /dev/null
+++ b/coreclr-git/patches/patch-src_vm_amd64_jithelpers__fast.S
@@ -0,0 +1,22 @@
+$NetBSD$
+
+--- src/vm/amd64/jithelpers_fast.S.orig	2016-05-03 01:25:01.000000000 +0000
++++ src/vm/amd64/jithelpers_fast.S
+@@ -110,7 +110,7 @@ LEAF_ENTRY JIT_WriteBarrier, _TEXT
+         movabs  rax, 0xF0F0F0F0F0F0F0F0
+ 
+         // Touch the card table entry, if not already dirty.
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         cmp     byte ptr [rdi + rax], 0FFh
+         .byte 0x75, 0x02
+         // jne     UpdateCardTable
+@@ -301,7 +301,7 @@ LEAF_ENTRY JIT_ByRefWriteBarrier, _TEXT
+ 
+         // Check if we need to update the card table
+         // Calc pCardByte
+-        shr     rcx, 0Bh
++        shr     rcx, 0x0B
+         PREPARE_EXTERNAL_VAR g_card_table, rax
+         add     rcx, [rax]
+ 
diff --git a/coreclr-git/patches/patch-src_vm_amd64_jithelpers__fastwritebarriers.S b/coreclr-git/patches/patch-src_vm_amd64_jithelpers__fastwritebarriers.S
new file mode 100644
index 0000000..61a113a
--- /dev/null
+++ b/coreclr-git/patches/patch-src_vm_amd64_jithelpers__fastwritebarriers.S
@@ -0,0 +1,58 @@
+$NetBSD$
+
+--- src/vm/amd64/jithelpers_fastwritebarriers.S.orig	2016-05-03 01:25:01.000000000 +0000
++++ src/vm/amd64/jithelpers_fastwritebarriers.S
+@@ -32,7 +32,7 @@ PATCH_LABEL JIT_WriteBarrier_PreGrow64_P
+         movabs  rax, 0xF0F0F0F0F0F0F0F0
+ 
+         // Touch the card table entry, if not already dirty.
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         cmp     byte ptr [rdi + rax], 0FFh
+         .byte 0x75, 0x02
+         // jne     UpdateCardTable_PreGrow64
+@@ -87,7 +87,7 @@ PATCH_LABEL JIT_WriteBarrier_PostGrow64_
+         movabs  rax, 0xF0F0F0F0F0F0F0F0
+ 
+         // Touch the card table entry, if not already dirty.
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         cmp     byte ptr [rdi + rax], 0FFh
+         .byte 0x75, 0x02
+         // jne     UpdateCardTable_PostGrow64
+@@ -125,7 +125,7 @@ LEAF_ENTRY JIT_WriteBarrier_SVR64, _TEXT
+ PATCH_LABEL JIT_WriteBarrier_SVR64_PatchLabel_CardTable
+         movabs  rax, 0xF0F0F0F0F0F0F0F0
+ 
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+ 
+         cmp     byte ptr [rdi + rax], 0FFh
+         .byte 0x75, 0x02
+@@ -178,7 +178,7 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_
+         // jb      Exit_WriteWatch_PreGrow64
+ 
+         // Touch the card table entry, if not already dirty.
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         NOP_2_BYTE // padding for alignment of constant
+ PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable
+         movabs  rax, 0xF0F0F0F0F0F0F0F0
+@@ -249,7 +249,7 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_
+         movabs  rax, 0xF0F0F0F0F0F0F0F0
+ 
+         // Touch the card table entry, if not already dirty.
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         cmp     byte ptr [rdi + rax], 0FFh
+         .byte 0x75, 0x02
+         // jne     UpdateCardTable_WriteWatch_PostGrow64
+@@ -304,7 +304,7 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_
+         mov     byte ptr [rax], 0FFh
+ 
+     CheckCardTable_WriteWatch_SVR64:
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         cmp     byte ptr [rdi + r11], 0FFh
+         .byte 0x75, 0x02
+         // jne     UpdateCardTable_WriteWatch_SVR64
diff --git a/coreclr-git/patches/patch-src_vm_amd64_jithelpers__slow.S b/coreclr-git/patches/patch-src_vm_amd64_jithelpers__slow.S
new file mode 100644
index 0000000..9396d3c
--- /dev/null
+++ b/coreclr-git/patches/patch-src_vm_amd64_jithelpers__slow.S
@@ -0,0 +1,18 @@
+$NetBSD$
+
+--- src/vm/amd64/jithelpers_slow.S.orig	2016-05-03 01:25:01.000000000 +0000
++++ src/vm/amd64/jithelpers_slow.S
+@@ -93,7 +93,7 @@ LEAF_ENTRY JIT_WriteBarrier_Debug, _TEXT
+ 
+         // Check if we need to update the card table
+         // Calc pCardByte
+-        shr     rdi, 0Bh
++        shr     rdi, 0x0B
+         PREPARE_EXTERNAL_VAR g_card_table, r10
+         add     rdi, [r10]
+ 
+@@ -111,4 +111,3 @@ LEAF_ENTRY JIT_WriteBarrier_Debug, _TEXT
+         REPRET
+ LEAF_END_MARKED JIT_WriteBarrier_Debug, _TEXT
+ #endif
+-
diff --git a/coreclr-git/patches/patch-tests_src_Interop_StructMarshalling_PInvoke_MarshalStructAsParamDLL.h b/coreclr-git/patches/patch-tests_src_Interop_StructMarshalling_PInvoke_MarshalStructAsParamDLL.h
new file mode 100644
index 0000000..f394f42
--- /dev/null
+++ b/coreclr-git/patches/patch-tests_src_Interop_StructMarshalling_PInvoke_MarshalStructAsParamDLL.h
@@ -0,0 +1,20 @@
+$NetBSD$
+
+--- tests/src/Interop/StructMarshalling/PInvoke/MarshalStructAsParamDLL.h.orig	2016-05-03 01:25:01.000000000 +0000
++++ tests/src/Interop/StructMarshalling/PInvoke/MarshalStructAsParamDLL.h
+@@ -787,7 +787,7 @@ void ChangeU(U* p)
+ 	p->uiPtr = (LPVOID)(64);
+ 	p->s = 32767;
+ 	p->us = 0;
+-	p->b = 255;
++	p->b = -1;
+ 	p->sb = -128;
+ 	p->l = -1234567890;
+ 	p->ul = 0;
+@@ -897,4 +897,4 @@ bool IsCorrectLongStructPack16Explicit(L
+ 	if(p->l1 != 32 || p->l2 != 32)
+ 		return false;
+ 	return true;
+-}
+\ No newline at end of file
++}


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