Re: kern/60144: virtio(4) cache coherence issue

[Jason Thorpe <thorpej%me.com@localhost>]

> On May 22, 2026, at 12:45 PM, Taylor R Campbell via gnats <gnats-admin%NetBSD.org@localhost> wrote:
> 
> I don't understand, why would avoiding writeback matter in PREREAD or
> POSTREAD?

It’s not a matter of avoiding write-back … you can’t avoid it, it’s the only way to invalidate a cache line on a 68040 (it’s wb-inv type operation).

The issue is where you do the write-back.  If you do it in POSTREAD, you could clobber the data you just got via DMA if a neighboring datum in the same cache line were modified by the CPU for some other reason.  If you do the write-back in PREREAD, there’s no danger of clobbering the datum you want to receive via DMA.

Some MIPS CPUs have similar cache behavior.

-- thorpej