Re: kern/60144: virtio(4) cache coherence issue

["Taylor R Campbell via gnats" <gnats-admin%NetBSD.org@localhost>]

The following reply was made to PR kern/60144; it has been noted by GNATS.

From: Taylor R Campbell <riastradh%NetBSD.org@localhost>
To: Jason Thorpe <thorpej%me.com@localhost>
Cc: Tetsuya Isaki <isaki%pastel-flower.jp@localhost>,
	Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>
	nick.hudson%gmx.co.uk@localhost, gnats-bugs%netbsd.org@localhost,
	kern-bug-people%netbsd.org@localhost, netbsd-bugs%netbsd.org@localhost, adrian%NetBSD.org@localhost
Subject: Re: kern/60144: virtio(4) cache coherence issue
Date: Fri, 22 May 2026 16:44:53 +0000

 > Date: Fri, 22 May 2026 08:31:20 -0400
 > From: Jason Thorpe <thorpej%me.com@localhost>
 >=20
 > > On May 18, 2026, at 7:30=E2=80=AFPM, Taylor R Campbell via gnats <gnats=
 -admin%NetBSD.org@localhost> wrote:
 > >=20
 > > But on others -- such as m68k, mips, and armv<7 -- POSTREAD alone
 > > isn't enough because it's a noop: these architectures assume that
 > > after PREREAD, the driver doesn't load the memory in question until
 > > the DMA read operation has completed, so flushing cached data in
 > > PREREAD and doing nothing in POSTREAD is enough to ensure that the
 > > driver's load isn't stale.
 >=20
 > This isn=E2=80=99t why.  The real reason is that the cache
 > implementation on some of these platforms does not have an
 > invalidate-without-writeback operation.
 
 I don't understand, why would avoiding writeback matter in PREREAD or
 POSTREAD?
 
 For PREREAD: If there are buffered stores to the memory in question,
 surely it shouldn't matter whether we have the CPU write them back or
 discard them, because the hardware device is going to overwrite the
 memory anyway?
 
 For POSTREAD: Surely, from the moment PREREAD returns, there should be
 no buffered stores pending from the CPU to the relevant part of
 memory?
 
 And if the driver issues any additional stores between PREREAD and
 POSTREAD, causing stores to get buffered so writeback would make a
 difference, isn't that a driver bug no matter what the cache
 architecture is?
 
 If there are cached _loads_, do _those_ get written back because the
 architecture doesn't distinguish cached loads from buffered stores, so
 invalidate-with-writeback on POSTREAD would clobber any updates made
 by the hardware device?