Re: kern/60144: virtio(4) cache coherence issue

["Jason Thorpe via gnats" <gnats-admin%NetBSD.org@localhost>]

The following reply was made to PR kern/60144; it has been noted by GNATS.

From: Jason Thorpe <thorpej%me.com@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: kern-bug-people%netbsd.org@localhost,
 gnats-admin%netbsd.org@localhost,
 netbsd-bugs%netbsd.org@localhost,
 isaki%pastel-flower.jp@localhost,
 "riastradh%netbsd.org@localhost" <riastradh%NetBSD.org@localhost>
Subject: Re: kern/60144: virtio(4) cache coherence issue
Date: Fri, 22 May 2026 21:55:39 -0400

 > On May 22, 2026, at 12:45=E2=80=AFPM, Taylor R Campbell via gnats =
 <gnats-admin%NetBSD.org@localhost> wrote:
 >=20
 > I don't understand, why would avoiding writeback matter in PREREAD or
 > POSTREAD?
 
 It=E2=80=99s not a matter of avoiding write-back =E2=80=A6 you can=E2=80=99=
 t avoid it, it=E2=80=99s the only way to invalidate a cache line on a =
 68040 (it=E2=80=99s wb-inv type operation).
 
 The issue is where you do the write-back.  If you do it in POSTREAD, you =
 could clobber the data you just got via DMA if a neighboring datum in =
 the same cache line were modified by the CPU for some other reason.  If =
 you do the write-back in PREREAD, there=E2=80=99s no danger of =
 clobbering the datum you want to receive via DMA.
 
 Some MIPS CPUs have similar cache behavior.
 
 -- thorpej