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Re: kern/49964: DRM/KMS panic with Radeon hardware

The following reply was made to PR kern/49964; it has been noted by GNATS.

From: coypu%SDF.ORG@localhost
Subject: Re: kern/49964: DRM/KMS panic with Radeon hardware
Date: Fri, 16 Oct 2015 23:49:53 +0000

 Apologies for the late response and some differences - I had compiled with a slightly different kernel (a slightly 
 newer -current). I don't think it matters, but if something is confusing, that is why.
 Thank you.
 Output from kernel panic:
 drm: initializing kernel modesetting (CEDAR 0x68E1 0x1028:0x466).
 drm: register mmio base: 0xfbe20000
 drm: register mmio size: 131072
 DRM error in igp_read_bios_from_vram:
 DRM error in igp_read_bios_from_vram:  bad-looking vbios or allocation failed
 DRM error in radeon_read_bios: pci_map_rom failed
 DRM error in radeon_read_bios: pci_map_rom failed
 DRM error in radeon_get_bios: Unable to locate a BIOS ROM
 : error: Fatal error during GPU init
 radeon0: unable to attach drm: 22
 panic: cnopen: no console device
 fatal breakpoint trap in supervisor mode
 trap type 1 code 0 rip ffffffff80281dc5 cs 8 rflags 246 cr2 7f7ff6c0cc00 ilevel
 0 rsp fffffe8045a0ead8
 curlwp 0xfffffe8045932a80 pid 2.1 lowest kstack 0xfffffe8045a0c2c0
 Stopped in pid 2.1 (init) at    netbsd:breakpoint+0x5:  leave
 this is the output of pcictl pci0 dump -b 001 -d 00 -f 0:
 PCI configuration registers:
   Common header:
     0x00: 0x68e11002 0x00100007 0x03000000 0x00000010
     Vendor Name: ATI Technologies (0x1002)
     Device ID: 0x68e1
     Command register: 0x0007
       I/O space accesses: on
       Memory space accesses: on
       Bus mastering: on
       Special cycles: off
       MWI transactions: off
       Palette snooping: off
       Parity error checking: off
       Address/data stepping: off
       System error (SERR): off
       Fast back-to-back transactions: off
       Interrupt disable: off
     Status register: 0x0010
       Interrupt status: inactive
       Capability List support: on
       66 MHz capable: off
       User Definable Features (UDF) support: off
       Fast back-to-back capable: off
       Data parity error detected: off
       DEVSEL timing: fast (0x0)
       Slave signaled Target Abort: off
       Master received Target Abort: off
       Master received Master Abort: off
       Asserted System Error (SERR): off
       Parity error detected: off
     Class Name: display (0x03)
     Subclass Name: VGA (0x00)
     Interface: 0x00
     Revision ID: 0x00
     BIST: 0x00
     Header Type: 0x00 (0x00)
     Latency Timer: 0x00
     Cache Line Size: 64bytes (0x10)
   Type 0 ("normal" device) header:
     0x10: 0xc000000c 0x00000000 0xfbe20004 0x00000000
     0x20: 0x0000e001 0x00000000 0x00000000 0x04661028
     0x30: 0xfbe00000 0x00000050 0x00000000 0x0000010b
     Base address register at 0x10
       type: 64-bit prefetchable memory
       base: 0x00000000c0000000, not sized
     Base address register at 0x18
       type: 64-bit nonprefetchable memory
       base: 0x00000000fbe20000, not sized
     Base address register at 0x20
       type: i/o
       base: 0x0000e000, not sized
     Base address register at 0x24
       not implemented(?)
     Cardbus CIS Pointer: 0x00000000
     Subsystem vendor ID: 0x1028
     Subsystem ID: 0x0466
     Expansion ROM Base Address: 0xfbe00000
     Capability list pointer: 0x50
     Reserved @ 0x38: 0x00000000
     Maximum Latency: 0x00
     Minimum Grant: 0x00
     Interrupt pin: 0x01 (pin A)
     Interrupt line: 0x0b
   Capability register at 0x50
     type: 0x01 (Power Management)
   Capability register at 0x58
     type: 0x10 (PCI Express)
   Capability register at 0xa0
     type: 0x05 (MSI)
   PCI Power Management Capabilities Register
     Capabilities register: 0x0603
       Version: 1.2
       PME# clock: off
       Device specific initialization: off
       3.3V auxiliary current: self-powered
       D1 power management state support: on
       D2 power management state support: on
       PME# support D0: off
       PME# support D1: off
       PME# support D2: off
       PME# support D3 hot: off
       PME# support D3 cold: off
     Control/status register: 0x0000
       Power state: D0
       PCI Express reserved: off
       No soft reset: off
       PME# assertion: disabled
       PME# status: off
     Bridge Support Extensions register: 0x00
       B2/B3 support: off
       Bus Power/Clock Control Enable: off
     Data register: 0x00
   PCI Message Signaled Interrupt
     Message Control register: 0x0080
       MSI Enabled: off
       Multiple Message Capable: no (1 vector)
       Multiple Message Enabled: off (1 vector)
       64 Bit Address Capable: on
       Per-Vector Masking Capable: off
     Message Address (lower) register: 0x00000000
     Message Address (upper) register: 0x00000000
     Message Data register: 0x00000000
   PCI Express Capabilities Register
     Capability register: 0012
       Capability version: 2
       Device type: Legacy PCI Express Endpoint device
       Slot implemented: off
       Interrupt Message Number: 0
     Device Capabilities Register: 0x00008fa1
       Max Payload Size Supported: 256 bytes max
       Phantom Functions Supported: not available
       Extended Tag Field Supported: 8bit
       Endpoint L0 Acceptable Latency: 2us - 4us
       Endpoint L1 Acceptable Latency: More than 64us
       Attention Button Present: off
       Attention Indicator Present: off
       Power Indicator Present: off
       Role-Based Error Report: on
       Captured Slot Power Limit Value: 0
       Captured Slot Power Limit Scale: 0
       Function-Level Reset Capability: off
     Device Control Register: 0x0800
       Correctable Error Reporting Enable: off
       Non Fatal Error Reporting Enable: off
       Fatal Error Reporting Enable: off
       Unsupported Request Reporting Enable: off
       Enable Relaxed Ordering: off
       Max Payload Size: 128 byte
       Extended Tag Field Enable: off
       Phantom Functions Enable: off
       Aux Power PM Enable: off
       Enable No Snoop: on
       Max Read Request Size: 128 byte
     Device Status Register: 0x0000
       Correctable Error Detected: off
       Non Fatal Error Detected: off
       Fatal Error Detected: off
       Unsupported Request Detected: off
       Aux Power Detected: off
       Transaction Pending: off
     Link Capabilities Register: 0x00000d01
       Maximum Link Speed: 2.5GT/s
       Maximum Link Width: x16 lanes
       Active State PM Support: L0s and L1 supported
       L0 Exit Latency: Less than 64ns
       L1 Exit Latency: Less than 1us
       Port Number: 0
       Clock Power Management: off
       Surprise Down Error Report: off
       Data Link Layer Link Active: off
       Link BW Notification Capable: off
       ASPM Optionally Compliance: off
     Link Control Register: 0x0043
       Active State PM Control: L0s and L1 Entry Enabled
       Read Completion Boundary Control: 64bytes
       Link Disable: off
       Retrain Link: off
       Common Clock Configuration: on
       Extended Synch: off
       Enable Clock Power Management: off
       Hardware Autonomous Width Disable: off
       Link Bandwidth Management Interrupt Enable: off
       Link Autonomous Bandwidth Interrupt Enable: off
     Link Status Register: 0x1101
       Negotiated Link Speed: 2.5GT/s
       Negotiated Link Width: x16 lanes
       Training Error: off
       Link Training: off
       Slot Clock Configuration: on
       Data Link Layer Link Active: off
       Link Bandwidth Management Status: off
       Link Autonomous Bandwidth Status: off
     Device Capabilities 2: 0x00000000
       Completion Timeout Ranges Supported: 0 
       Completion Timeout Disable Supported: off
       ARI Forwarding Supported: off
       AtomicOp Routing Supported: off
       32bit AtomicOp Completer Supported: off
       64bit AtomicOp Completer Supported: off
       128-bit CAS Completer Supported: off
       No RO-enabled PR-PR passing: off
       LTR Mechanism Supported: off
       TPH Completer Supported: 0
       OBFF Supported: Not supported
       Extended Fmt Field Supported: off
       End-End TLP Prefix Supported: off
       Max End-End TLP Prefixes: 0
     Device Control 2: 0x0000
       Completion Timeout Value: 50us to 50ms
       Completion Timeout Disabled: off
       ARI Forwarding Enabled: off
       AtomicOp Rquester Enabled: off
       AtomicOp Egress Blocking: off
       IDO Request Enabled: off
       IDO Completion Enabled: off
       LTR Mechanism Enabled: off
       OBFF: Disabled
       End-End TLP Prefix Blocking on: off
     Link Capabilities 2: 0x00000000
       Supported Link Speed Vector:
       Crosslink Supported: off
     Link Control 2: 0x0001
       Target Link Speed: 2.5GT/s
       Enter Compliance Enabled: off
       HW Autonomous Speed Disabled: off
       Selectable De-emphasis: off
       Transmit Margin: 0
       Enter Modified Compliance: off
       Compliance SOS: off
       Compliance Present/De-emphasis: 0
     Link Status 2: 0x0000
       Current De-emphasis Level: off
       Equalization Complete: off
       Equalization Phase 1 Successful: off
       Equalization Phase 2 Successful: off
       Equalization Phase 3 Successful: off
       Link Equalization Request: off
   Device-dependent header:
     0x40: 0x00000000 0x00000000 0x00000000 0x04661028
     0x50: 0x06035801 0x00000000 0x0012a010 0x00008fa1
     0x60: 0x00000800 0x00000d01 0x11010043 0x00000000
     0x70: 0x00000000 0x00000000 0x00000000 0x00000000
     0x80: 0x00000000 0x00000000 0x00000001 0x00000000
     0x90: 0x00000000 0x00000000 0x00000000 0x00000000
     0xa0: 0x00800005 0x00000000 0x00000000 0x00000000
     0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xf0: 0x00000000 0x00000000 0x00000000 0x00000000

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