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Re: enhanced speed step on AMD64
On Mon, May 24, 2010 at 10:02:59AM -0700, Brian Buhrow wrote:
> Hello. How hard would it be to implement #3 of your description? Is
> it getting easier as our acpi implementation matures and becomes more
> stable and sophisticated?
Not that hard.
> On May 24, 2:03pm, Joerg Sonnenberger wrote:
> } Subject: Re: enhanced speed step on AMD64
> } On Mon, May 24, 2010 at 12:12:45AM +0000, bch%methodlogic.net@localhost
> } > Can anybody describe where "we" are at for supporting speedstep on CPUs
> } > like the i7, then? Will it require an entire new framework to support? Can
> } > somebody describe where the "problem" exists between this hardware and
> } > the current NetBSD support for Speedstep on it? I'm interested both for
> } > the practical matter of getting this CPU supported, and it's something
> } > I just don't know anything about, so a "teachable moment" :)
> } Basically, frequency changes in Intel-land done in one of three ways:
> } (1) The original Speed Step. The frequency changes are done by magic
> } calls into the BIOS and (AFAIK) a function of the chipset.
> } (2) EST until ~Core 2. Frequency and voltage are tabularised (older
> } CPUs) or derived algorithmically from certain MSR (machine status
> } registers). Change of the performance settings is done via MSR under
> } application control.
> } (3) EST since late Core2. The MSRs are mostly discontinued and/or
> } provide junk data. The kernel is supposed to use the ACPI Processor
> } object and its method for this purpose. Doesn't work for all older model
> } as it was often left out.
> } At the moment, (2) works best for the CPUs it can work on. (1) might or
> } might not work. (3) is not supported.
> } Joerg
> >-- End of excerpt from Joerg Sonnenberger
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