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Re: OpenBlockS600 (AMCC 405EX)

Hi there,

KIYOHARA Takashi wrote:

> Plathome's OpenBlockS600 (AMCC 405EX) boots on NFS.

Good work!

> I corrected emac. A lot of 4xx has one MAL and two EMAC.
> Moreover, 405EX uses a quite different interrupt line in EMAC and MAL.  It
> is not sequential.  Then, so as not to use the interrupt of MAL, I changed.
> However, this caused strange interrupt.  There might not be interrupt of
> the reception completion.
> I have the possibility of requesting the interrupt of MAL from opb in the
> future.
> Next, I will support UIC1 and UIC2.  This work has the possibility that a
> similar file such as include/ibm4xx/dcr405xx.h and include/ibm4xx/dcr405gp.h
> becomes a trouble.

I've only run a quick eye over the patch, but don't see any major
problems.  A couple of questions so far:

1: I haven't looked closely enough, but I suspect the 440 emac support is
   theoretical only?  If so, maybe better to separate out the devices that
   have been tested compared with those that haven't

+ * emac(4) supports following ibm4xx's EMACs.
+ *   XXXX: ZMII and 'TCP Accelaration Hardware' not support yet...
+ *
+ * 405EP       10/100 x2
+ * 405EX/EXr   10/100/1000 x2 (EXr x1), STA v2, 8 hash-Table, MAL v2, RGMII
+ * 405GP/GPr   10/100
+ * 440EP       10/100 x2, ZMII
+ * 440GP       10/100 x2, MAL v2, ZMII
+ * 440GX       10/100/1000 x4, MAL v2, ZMII/RGMII(ch 2, 3), TAH(ch 2, 3)
+ * 440SP       10/100/1000, MAL v2
+ * 440SPe      10/100/1000, STA v2, MAL v2
+ */

2: Related to the above, you test for OPB_FLAGS_EMAC_STACV2 only inside a
   OPB_FLAGS_EMAC_GBE block, but from memory the 10/100 MACs on the 440GX
   still use the new format registers.

3: I assume you tested the updated emac code on a machine with an older emac 
   (like a 405GP)? :)  I can dig out a 405GP Walnut if you want that tested
   and can't do so yourself.


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