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Re: HP ProLiant BL460c G1 boot failure
On Wed, 3 Sep 2008, Manuel Bouyer wrote:
One: I assume "SerDes controllers are not supported!" means that
the driver doesn't support fibre-optic versions of this device.
Is there a particular reason this isn't supported in our driver? It
I guess, because this is a port from the OpenBSD driver, and it didn't
support SerDes at that time.
The following changes (also from the OpenBSD driver) fixed this for me
on a Dell M600 blade server:
Index: sys/dev/pci/if_bnx.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_bnx.c,v
retrieving revision 1.18
diff -u -r1.18 if_bnx.c
--- sys/dev/pci/if_bnx.c 7 Feb 2008 01:21:55 -0000 1.18
+++ sys/dev/pci/if_bnx.c 3 Sep 2008 15:24:08 -0000
@@ -40,7 +40,7 @@
/*
* The following controllers are supported by this driver:
* BCM5706C A2, A3
- * BCM5708C B1
+ * BCM5708C B1, B2
*
* The following controllers are not supported by this driver:
* (These are not "Production" versions of the controller.)
@@ -412,6 +412,7 @@
u_int32_t command;
struct ifnet *ifp;
u_int32_t val;
+ int mii_flags = MIIF_FORCEANEG;
pcireg_t memtype;
bp = bnx_lookup(pa);
@@ -485,12 +486,6 @@
goto bnx_attach_fail;
}
- if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) {
- aprint_error_dev(sc->bnx_dev,
- "SerDes controllers are not supported!\n");
- goto bnx_attach_fail;
- }
-
/*
* Find the base address for shared memory access.
* Newer versions of bootcode use a signature and offset
@@ -610,16 +605,16 @@
/*
* The copper based NetXtreme II controllers
- * use an integrated PHY at address 1 while
- * the SerDes controllers use a PHY at
- * address 2.
+ * that support 2.5Gb operation (currently
+ * 5708S) use a PHY at address 2, otherwise
+ * the PHY is present at address 1.
*/
sc->bnx_phy_addr = 1;
if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) {
sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG;
sc->bnx_flags |= BNX_NO_WOL_FLAG;
- if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) {
+ if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) {
sc->bnx_phy_addr = 2;
val = REG_RD_IND(sc, sc->bnx_shmem_base +
BNX_SHARED_HW_CFG_CONFIG);
@@ -628,12 +623,6 @@
}
}
- if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) {
- aprint_error_dev(sc->bnx_dev,
- "SerDes is not supported by this driver!\n");
- goto bnx_attach_fail;
- }
-
/* Allocate DMA memory resources. */
sc->bnx_dmatag = pa->pa_dmat;
if (bnx_dma_alloc(sc)) {
@@ -652,10 +641,6 @@
ifp->if_init = bnx_init;
ifp->if_timer = 0;
ifp->if_watchdog = bnx_watchdog;
- if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG)
- ifp->if_baudrate = IF_Gbps(2.5);
- else
- ifp->if_baudrate = IF_Gbps(1);
IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1);
IFQ_SET_READY(&ifp->if_snd);
memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
@@ -686,8 +671,10 @@
sc->bnx_ec.ec_mii = &sc->bnx_mii;
ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange,
ether_mediastatus);
+ if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG)
+ mii_flags |= MIIF_HAVEFIBER;
mii_attach(self, &sc->bnx_mii, 0xffffffff,
- MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG);
+ MII_PHY_ANY, MII_OFFSET_ANY, mii_flags);
if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) {
aprint_error_dev(self, "no PHY found!\n");
@@ -994,28 +981,53 @@
{
struct bnx_softc *sc = device_private(dev);
struct mii_data *mii = &sc->bnx_mii;
+ int val;
- BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT);
+ val = REG_RD(sc, BNX_EMAC_MODE);
+ val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX |
+ BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK |
+ BNX_EMAC_MODE_25G);
- /* Set MII or GMII inerface based on the speed negotiated by the PHY. */
- if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
- DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n");
- BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII);
- } else {
- DBPRINT(sc, BNX_INFO, "Setting MII interface.\n");
- BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII);
+ /* Set MII or GMII interface based on the speed
+ * negotiated by the PHY.
+ */
+ switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ case IFM_10_T:
+ if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) {
+ DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n");
+ val |= BNX_EMAC_MODE_PORT_MII_10;
+ break;
+ }
+ /* FALLTHROUGH */
+ case IFM_100_TX:
+ DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n");
+ val |= BNX_EMAC_MODE_PORT_MII;
+ break;
+ case IFM_2500_SX:
+ DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n");
+ val |= BNX_EMAC_MODE_25G;
+ /* FALLTHROUGH */
+ case IFM_1000_T:
+ case IFM_1000_SX:
+ DBPRINT(sc, BNX_INFO, "Enablinb GMII interface.\n");
+ val |= BNX_EMAC_MODE_PORT_GMII;
+ break;
+ default:
+ val |= BNX_EMAC_MODE_PORT_GMII;
+ break;
}
/* Set half or full duplex based on the duplicity
* negotiated by the PHY.
*/
- if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
- DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n");
- BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX);
- } else {
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n");
- BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX);
+ val |= BNX_EMAC_MODE_HALF_DUPLEX;
+ } else {
+ DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n");
}
+
+ REG_WR(sc, BNX_EMAC_MODE, val);
}
/****************************************************************************/
@@ -4305,7 +4317,7 @@
{
struct bnx_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
- struct mii_data *mii;
+ struct mii_data *mii = &sc->bnx_mii;
int s, error = 0;
s = splnet();
@@ -4331,14 +4343,7 @@
DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n",
sc->bnx_phy_flags);
- if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG)
- error = ifmedia_ioctl(ifp, ifr,
- &sc->bnx_ifmedia, command);
- else {
- mii = &sc->bnx_mii;
- error = ifmedia_ioctl(ifp, ifr,
- &mii->mii_media, command);
- }
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
break;
default:
@@ -4825,8 +4830,6 @@
/* Schedule the next tick. */
callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc);
- /* DRC - ToDo: Add SerDes support and check SerDes link here. */
-
mii = &sc->bnx_mii;
mii_tick(mii);
--
Michael L. Hitch mhitch%montana.edu@localhost
Computer Consultant
Information Technology Center
Montana State University Bozeman, MT USA
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