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jmide/ahci/interrupt panic on boot
Has anyone else seen this or have any idea what might be going
on? Some debugging code shows that chp->ch_queue is null, but from
the code it looks like it should be set in ahci_attach. This was
working fine in 4.99.55 around March 10.
Thanks.
Gary Duzan
NetBSD 4.99.58 (CAPO64) #26: Sun Apr 6 11:28:08 EDT 2008
gary@capo:/usr/obj/sys/arch/amd64/compile.amd64/CAPO64
[ ... ]
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0
pchb0: Acer Labs product 0x1695 (rev. 0x00)
ppb0 at pci0 dev 1 function 0: Acer Labs product 0x524b (rev. 0x00)
pci1 at ppb0 bus 1
pci1: memory space enabled, rd/line, wr/inv ok
ppb1 at pci0 dev 2 function 0: Acer Labs product 0x524c (rev. 0x00)
pci2 at ppb1 bus 2
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
jmide0 at pci2 dev 0 function 0: JMicron Technology JMB363 SATA/PATA controller
jmide0: 1 PATA port, 2 SATA ports
jmide0: interrupting at ioapic1 pin 6 (irq 11)
ahcisata0 at jmide0
ahcisata0: AHCI revision 1.0, 2 ports, 32 command slots, features 0xc722e000
atabus0 at ahcisata0 channel 0
atabus1 at ahcisata0 channel 1
jmide0: PCI IDE interface used
jmide0: bus-master DMA support present
jmide0: primary channel wired to native-PCI mode
jmide0: primary channel is unused
jmide0: secondary channel wired to native-PCI mode
jmide0: secondary channel is PATA
atabus2 at jmide0 channel 1
ppb2 at pci0 dev 3 function 0: Acer Labs product 0x524d (rev. 0x00)
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled, rd/line, wr/inv ok
jmide1 at pci3 dev 0 function 0: JMicron Technology JMB360 SATA controller
jmide1: 1 SATA port
jmide1: interrupting at ioapic1 pin 11 (irq 5)
ahcisata1 at jmide1
ahcisata1: AHCI revision 1.0, 1 ports, 32 command slots, features 0xc722e000
atabus3 at ahcisata1 channel 0
pchb1 at pci0 dev 4 function 0
pchb1: Acer Labs M1689 Host-PCI Bridge (rev. 0x00)
[ ... ]
ahcisata1 port 0: device present, speed: 3.0Gb/s
uvm_fault(0xffffffff807094a0, 0x0, 1) -> e
ahci_intr_port() at netbsd:ahci_intr_port+0x29
ahci_intr() at netbsd:ahci_intr+0xaf
jmide_intr() at netbsd:jmide_intr+0x28
intr_biglock_wrapper() at netbsd:intr_biglock_wrapper+0x1d
Xintr_legacy5() at netbsd:Xintr_legacy5+0x103
--- interrupt ---
_kernel_lock() at netbsd:_kernel_lock+0xb2
===========================================================================
(gdb) list *(jmide_intr+0x28)
0xffffffff803b82c8 is in jmide_intr (/usr/src/sys/dev/pci/jmide.c:303).
298 struct jmide_softc *sc = arg;
299 int ret = 0;
300
301 #ifdef NJMAHCI
302 if (sc->sc_ahci)
303 ret |= ahci_intr(sc->sc_ahci);
304 #endif
305 if (sc->sc_npata)
306 ret |= pciide_pci_intr(&sc->sc_pciide);
307 return ret;
(gdb) list *(ahci_intr+0xaf)
0xffffffff801d036f is in ahci_intr (/usr/src/sys/dev/ic/ahcisata_core.c:425).
420 DEBUG_INTR);
421 r = 1;
422 AHCI_WRITE(sc, AHCI_IS, is);
423 for (i = 0; i < AHCI_MAX_PORTS; i++)
424 if (is & (1 << i))
425 ahci_intr_port(sc, &sc->sc_channels[i]);
426 }
427 return r;
428 }
429
(gdb) list *(ahci_intr_port+0x29)
0xffffffff801cfac9 is in ahci_intr_port
(/usr/src/sys/dev/ic/ahcisata_core.c:435).
430 void
431 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
432 {
433 u_int32_t is, tfd;
434 struct ata_channel *chp = &achp->ata_channel;
435 struct ata_xfer *xfer = chp->ch_queue->active_xfer;
436 int slot;
437
438 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
439 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
(gdb)
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