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Re: msk(4) require to sync status buffer
> > Then why do you think PREREAD/PREWRITE ops are requied here?
> The reason is that the msk driver clears SK_Y2_STOPC_OWN, and the DMA
> buffer is returned to LSI. And, LSI writes status reading that
> SK_Y2_STOPC_OWN is clear.
That doesn't mean PREREAD/PREWRITE are required there.
PREREAD/PREWRITE don't mean cache flush, as I said before.
You should call bus_dmamap_sync(9) as API.
> > As noted in the previous mail, if there is no WRITE op
> > (DMA xfer from CPU to device), POSTWRITE is not needed here.
> > (though POSTWRITE is no-op on most implemetation)
> I think that it should do POSTREAD/POSTWRITE here because we are doing
> PREREAD/PREWRITE beforehand.
Then is PREWRITE actually required there?
> > Strictly speaking, PREREAD or PREWRITE don't imply cache ops.
> > We should call bus_dmamap_sync(9) ops as defined in its API,
> > i.e. PREREAD/PREWRITE should be called before DMA started
> > and POSTREAD/POSTWRITE should be called after DMA xfer.
> The DMA transfer of the status buffer that we had read at the end was not
> completed. And status is sure to be written to this buffer at next.
If DMA is still being processed, we should call POSTREAD/POSTWRITE
just before CPU fetch and do PREREAD/PREWRITE right after CPU fetch
as per API.
> And, this buffer might be cached on the memory. In a word, it is
> necessary to invalidate.
Again, PREREAD/PREWRITE doesn't mean invalidate/writeback cache.
It's opaque op and implementation dependent.
Furthermore, on some architecbure invalidate can't be done
without writeback. Even if your architecbure supports
invalidate without writeback, you can't use invalidate
(and have to use invalidate and writeback) if buffer isn't
cacheline aligned. In that case, if you defer PREREAD calls
(which might do writeback and invalidate), you might lost
some DMA'ed data by CPU writeback.
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