On 23/07/2025 18:34, PHO wrote:
On 7/24/25 00:49, Robert Swindells wrote:
[snip]
Do you get core files left behind in the package working directory from running the bootstrap JVM?Yes I do. core: https://akari.cielonegro.org/tmp/java.core.gz crash log: https://akari.cielonegro.org/tmp/hs_err_pid1030.log I can reliably reproduce the SIGILL by doing this: % cd /usr/pkgsrc/lang/openjdk17 % make patch % LD_LIBRARY_PATH=./work/bootstrap/lib ./work/bootstrap/bin/java -h The offending code looks completely normal to me:0x0000f91ce30fddc8: add x0, x24, #0x0 // <- CRASHES HERE 0x0000f91ce30fddcc: mov x2, #0x0 // #0 0x0000f91ce30fddd0: ldr x8, [x0] 0x0000f91ce30fddd4: cbz x8, 0xf91ce30fdddc 0x0000f91ce30fddd8: mov x2, x0 0x0000f91ce30fdddc: mov x0, #0xe7bc // #59324 0x0000f91ce30fdde0: movk x0, #0xe30b, lsl #16 0x0000f91ce30fdde4: movk x0, #0xf91c, lsl #32 0x0000f91ce30fdde8: ret
I guess the code generation isn't sync'd correctly and the icache is stale The Arm ARM has this example. ; Coherency example for data and instruction accesses within the same ; Inner Shareable domain. ; Enter this code with ‹Wt> containing a new 32-bit instruction, ; to be held in Cacheable space at a location pointed to by Xn. STR Wt, [Xn] DC CVAU, Xn ; Clean data cache by VA to point of unification (PoU) DSB ISH ; Ensure visibility of the data cleaned from cache IC IVAU, Xn ; Invalidate instruction cache by VA to PoU DSB ISH ; Ensure completion of the invalidations ISB ; Synchronize the fetched instruction stream Nick