Hi, On 2025/05/12 0:21, Taylor R Campbell wrote:
Date: Sun, 11 May 2025 13:00:33 +0900 From: Rin Okuyama <rokuyama.rk%gmail.com@localhost> ``` 0x05e89a2c <+204>: ldrex r2, [r4] ... 0x05e89a3c <+220>: mcr 15, 0, r0, cr7, cr10, {5} 0x05e89a40 <+224>: strex r1, r3, [r4] 0x05e89a44 <+228>: cmp r1, #0 0x05e89a48 <+232>: bne 0x5e89a0c ``` Here, `mcr ...` is armv6 variant of `dmb`, which is dropped for armv8, and emulated by illegal insn handler; reservation made by `strex` is lost and `strex` always fails unconditionally.Can you try running this on a kernel with SCTLR_EL1.CP15BEN enabled? https://nxr.netbsd.org/xref/src/sys/arch/aarch64/aarch64/locore.S?r=1.95#1000 Just move it from the sctlr_clear bits to the sctlr_set bits. (On Linux there is a sysctl-equivalent for toggling this at runtime, abi.cp15_barrier: https://www.kernel.org/doc/Documentation/arm64/legacy_instructions.txt) I believe this is an llvm code generation bug (https://github.com/llvm/llvm-project/issues/41201) but until llvm fixes it (or we patch llvm -- and, perhaps, rust-internal-llvm -- to fix it), this might help to make progress on armv8 hardware if it still supports this MCR instruction (CP15DMB).
Thank you very much for your analysis! At least for Cortex-A72 (HoneyComb LX2K), SCTLR_EL1.CP15BEN can be enabled, and lang/rust successfully built :) rin