tech-kern archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
agp_nvidia port for review
Hi,
I've ported the NVIDIA nForce AGP controller driver (agp_nvidia) from
FreeBSD to NetBSD. The driver supports the nForce and nForce2 chipsets
(PCI IDs 0x01a4 and 0x01e0). Before committing the code, I would like
to hear any reviews, comments, or objections, so I will wait for some
time.
PR can be found: https://github.com/vezhlys/netbsd-src/pull/4/changes,
full diff is also attached.
My motivation was quite simple:
* I have an nForce2 board and this was a relatively straightforward port
* AGP mode may offer performance benefits for some GPUs
* FreeBSD is deprecating i386 and AGP support, making this a good time
to bring it into NetBSD
The port is more or less 1:1 with the FreeBSD driver, which was itself
written following the Linux counterpart (I believe).
Testing was tricky on the actual hardware. radeon(4) stalled when AGP
was attached, this turned out to be a general radeon DRM issue with
AGP cards. Linux works around this by defaulting radeon_agpmode to -1
globally (forcing PCI mode for GART). nouveau(4) probably manages its
own GART internally and does not call into agpgart's
bind/unbind/flush_tlb path directly. Same goes to R128 AGP, it uses
llvmpipe, and I probably lack libraries for the 3D acceleration.
To test these functions, I used a small test program to poke
/dev/agpgart via ioctls. bind_page, unbind_page, and flush_tlb seems
to work correctly; the nForce2 WBC flush completes immediately.
Detach function is compile-tested but disabled now with #if 0 guards,
consistent with other AGP drivers.
FreeBSD driver link:
https://raw.githubusercontent.com/freebsd/freebsd-src/refs/heads/main/sys/dev/agp/agp_nvidia.c
Linux driver:
https://raw.githubusercontent.com/torvalds/linux/refs/heads/master/drivers/char/agp/nvidia-agp.c
Thanks!
Regards,
Andrius V
diff --git a/share/man/man4/agp.4 b/share/man/man4/agp.4
index 2a522341260a..4b35e91ee2ef 100644
--- a/share/man/man4/agp.4
+++ b/share/man/man4/agp.4
@@ -27,7 +27,7 @@
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
-.Dd October 3, 2010
+.Dd June 7, 2026
.Dt AGP 4
.Os
.Sh NAME
@@ -63,6 +63,8 @@ AMD 751 and 761 host-to-AGP bridges
.It
Intel 82810, 82810-DC100, 82810E, and 82815 SVGA controllers
.It
+NVIDIA nForce and nForce2 AGP controllers, nForce 3 host-to-AGP bridges
+.It
SiS 5591 host-to-AGP bridge
.It
VIA
diff --git a/sys/arch/x86/pci/files.pci b/sys/arch/x86/pci/files.pci
index b280f47e32b8..1889d46ad6ef 100644
--- a/sys/arch/x86/pci/files.pci
+++ b/sys/arch/x86/pci/files.pci
@@ -6,7 +6,7 @@ file arch/x86/pci/aapic.c aapic
file arch/x86/pci/agp_machdep.c agp
-define agp_x86: agp_ali, agp_amd, agp_amd64, agp_i810, agp_intel, agp_sis, agp_via
+define agp_x86: agp_ali, agp_amd, agp_amd64, agp_i810, agp_intel, agp_nvidia, agp_sis, agp_via
defflag AGP_X86
# PCI-Host bridge chipsets
diff --git a/sys/dev/pci/agp.c b/sys/dev/pci/agp.c
index 8714bed22f0f..52ea7b14202b 100644
--- a/sys/dev/pci/agp.c
+++ b/sys/dev/pci/agp.c
@@ -111,6 +111,7 @@ static bool agp_resume(device_t, const pmf_qual_t *);
#include "agp_amd.h"
#include "agp_i810.h"
#include "agp_intel.h"
+#include "agp_nvidia.h"
#include "agp_sis.h"
#include "agp_via.h"
#include "agp_amd64.h"
@@ -228,6 +229,13 @@ const struct agp_product {
agp_amd64_match, agp_amd64_attach },
#endif
+#if NAGP_NVIDIA > 0
+ { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB,
+ NULL, agp_nvidia_attach },
+ { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB,
+ NULL, agp_nvidia_attach },
+#endif
+
#if NAGP_AMD64 > 0
{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_755,
agp_amd64_match, agp_amd64_attach },
diff --git a/sys/dev/pci/agp_nvidia.c b/sys/dev/pci/agp_nvidia.c
new file mode 100644
index 000000000000..386ab270cc86
--- /dev/null
+++ b/sys/dev/pci/agp_nvidia.c
@@ -0,0 +1,396 @@
+/* $NetBSD$ */
+
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2003 Matthew N. Dodd <winter%jurai.net@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/proc.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/agpio.h>
+
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/agpvar.h>
+#include <dev/pci/agpreg.h>
+
+#include <machine/cpufunc.h>
+
+#include <sys/bus.h>
+
+#define AGP_NFORCE_MEMCTLTAG(pc, dev) pci_make_tag(pc, 0, 0, dev)
+#define AGP_NFORCE_PPBTAG(pc) pci_make_tag(pc, 0, 30, 0)
+
+#define SYSCFG 0xC0010010
+#define IORR_BASE0 0xC0010016
+#define IORR_MASK0 0xC0010017
+#define AMD_K7_NUM_IORR 2
+
+struct agp_nvidia_softc {
+ struct agp_softc agp;
+ u_int32_t initial_aperture; /* aperture size at startup */
+ struct agp_gatt * gatt;
+
+ device_t dev; /* AGP Controller */
+ pcitag_t mc1_tag; /* memory controller func 1 */
+ pcitag_t mc2_tag; /* memory controller func 2 */
+ pcitag_t bdev_tag; /* Bridge */
+
+ u_int32_t wbc_mask;
+ int num_dirs;
+ int num_active_entries;
+ off_t pg_offset;
+};
+
+
+static int agp_nvidia_init(struct agp_softc *);
+static u_int32_t agp_nvidia_get_aperture(struct agp_softc *);
+static int agp_nvidia_set_aperture(struct agp_softc *, u_int32_t);
+static int agp_nvidia_bind_page(struct agp_softc *, off_t, bus_addr_t);
+static int agp_nvidia_unbind_page(struct agp_softc *, off_t);
+static void agp_nvidia_flush_tlb(struct agp_softc *);
+#if 0
+static int agp_nvidia_detach(struct agp_softc *);
+#endif
+static int nvidia_init_iorr(u_int32_t, u_int32_t);
+
+
+static struct agp_methods agp_nvidia_methods = {
+ agp_nvidia_get_aperture,
+ agp_nvidia_set_aperture,
+ agp_nvidia_bind_page,
+ agp_nvidia_unbind_page,
+ agp_nvidia_flush_tlb,
+ agp_generic_enable,
+ agp_generic_alloc_memory,
+ agp_generic_free_memory,
+ agp_generic_bind_memory,
+ agp_generic_unbind_memory,
+};
+
+int
+agp_nvidia_attach(device_t parent, device_t self, void *aux)
+{
+ struct agp_softc *sc = device_private(self);
+ struct pci_attach_args *pa = aux;
+ struct agp_nvidia_softc *nsc;
+ struct agp_gatt *gatt;
+
+ nsc = malloc(sizeof *nsc, M_AGP, M_WAITOK);
+
+ switch (PCI_PRODUCT(pa->pa_id)) {
+ case PCI_PRODUCT_NVIDIA_NFORCE_PCHB:
+ nsc->wbc_mask = AGP_NVIDIA_NFORCE_WBC_MASK;
+ break;
+ case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB:
+ nsc->wbc_mask = AGP_NVIDIA_NFORCE2_WBC_MASK;
+ break;
+ default:
+ /* Should never happen */
+ aprint_error_dev(self, "Bad chip id\n");
+ return ENODEV;
+ }
+
+ sc->as_chipc = nsc;
+ sc->as_methods = &agp_nvidia_methods;
+ nsc->mc1_tag = AGP_NFORCE_MEMCTLTAG(pa->pa_pc, 1);
+ nsc->mc2_tag = AGP_NFORCE_MEMCTLTAG(pa->pa_pc, 2);
+ nsc->bdev_tag = AGP_NFORCE_PPBTAG(pa->pa_pc);
+
+ pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
+ NULL);
+
+ if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
+ aprint_error(": can't map aperture\n");
+ free(nsc, M_AGP);
+ sc->as_chipc = NULL;
+ return ENXIO;
+ }
+
+ nsc->initial_aperture = AGP_GET_APERTURE(sc);
+
+ for (;;) {
+ gatt = agp_alloc_gatt(sc);
+ if (gatt)
+ break;
+
+ /*
+ * Probably contigmalloc failure. Try reducing the
+ * aperture so that the gatt size reduces.
+ */
+ if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
+ agp_generic_detach(sc);
+ aprint_error(": failed to set aperture\n");
+ return ENOMEM;
+ }
+ }
+ nsc->gatt = gatt;
+
+ return agp_nvidia_init(sc);
+}
+
+static int
+agp_nvidia_init(struct agp_softc *sc)
+{
+ struct agp_nvidia_softc *nsc = sc->as_chipc;
+ struct agp_gatt *gatt = nsc->gatt;
+ u_int32_t apbase;
+ u_int32_t aplimit;
+ u_int32_t temp;
+ int size, i, error;
+
+ apbase = sc->as_apaddr;
+ aplimit = apbase + AGP_GET_APERTURE(sc) - 1;
+ pci_conf_write(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_APBASE, apbase);
+ pci_conf_write(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_APLIMIT, aplimit);
+ pci_conf_write(sc->as_pc, nsc->bdev_tag, AGP_NVIDIA_3_APBASE, apbase);
+ pci_conf_write(sc->as_pc, nsc->bdev_tag, AGP_NVIDIA_3_APLIMIT, aplimit);
+
+ error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(sc));
+ error = 0;
+ if (error) {
+ aprint_error_dev(sc->as_dev, "Failed to setup IORRs\n");
+ agp_generic_detach(sc);
+ return ENOMEM;
+ }
+
+ /* directory size is 64k */
+ size = AGP_GET_APERTURE(sc) / 1024 / 1024;
+ nsc->num_dirs = size / 64;
+ nsc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
+ nsc->pg_offset = 0;
+ if (nsc->num_dirs == 0) {
+ nsc->num_dirs = 1;
+ nsc->num_active_entries /= (64 / size);
+ nsc->pg_offset = rounddown2(apbase & (64 * 1024 * 1024 - 1),
+ AGP_GET_APERTURE(sc)) / PAGE_SIZE;
+ }
+
+ /* (G)ATT Base Address */
+ for (i = 0; i < 8; i++) {
+ pci_conf_write(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_ATTBASE(i),
+ (gatt->ag_physical + (i % nsc->num_dirs) * 64 * 1024) | 1);
+ }
+
+ /* GTLB Control */
+ temp = pci_conf_read(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL);
+ pci_conf_write(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL, temp | 0x11);
+
+ /* GART Control */
+ temp = pci_conf_read(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE);
+ pci_conf_write(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE, temp | 0x100);
+
+ return 0;
+}
+
+static u_int32_t
+agp_nvidia_get_aperture(struct agp_softc *sc)
+{
+ int val;
+
+ val = (int) pci_conf_read(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE) & 0xff;
+ switch (val) {
+ case 0: return (512 * 1024 * 1024);
+ case 8: return (256 * 1024 * 1024);
+ case 12: return (128 * 1024 * 1024);
+ case 14: return (64 * 1024 * 1024);
+ case 15: return (32 * 1024 * 1024);
+ default:
+ aprint_error_dev(sc->as_dev, "Invalid aperture setting 0x%x\n", val);
+ return 0;
+ }
+}
+
+static int
+agp_nvidia_set_aperture(struct agp_softc *sc, u_int32_t aperture)
+{
+ u_int8_t key;
+ pcireg_t reg;
+
+ switch (aperture) {
+ case (512 * 1024 * 1024): key = 0; break;
+ case (256 * 1024 * 1024): key = 8; break;
+ case (128 * 1024 * 1024): key = 12; break;
+ case (64 * 1024 * 1024): key = 14; break;
+ case (32 * 1024 * 1024): key = 15; break;
+ default:
+ aprint_error_dev(sc->as_dev, "Invalid aperture size (%dMb)\n",
+ aperture / 1024 / 1024);
+ return EINVAL;
+ }
+
+ reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE);
+ reg = (reg & ~0x0f) | key;
+ pci_conf_write(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE, reg);
+ return 0;
+}
+
+static int
+agp_nvidia_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
+{
+ struct agp_nvidia_softc *nsc = sc->as_chipc;
+ u_int32_t index;
+
+ if (offset >= (nsc->gatt->ag_entries << AGP_PAGE_SHIFT))
+ return EINVAL;
+
+ index = (nsc->pg_offset + offset) >> AGP_PAGE_SHIFT;
+ nsc->gatt->ag_virtual[index] = physical | 1;
+
+ return 0;
+}
+
+static int
+agp_nvidia_unbind_page(struct agp_softc *sc, off_t offset)
+{
+ struct agp_nvidia_softc *nsc = sc->as_chipc;
+ u_int32_t index;
+
+ if (offset >= (nsc->gatt->ag_entries << AGP_PAGE_SHIFT))
+ return EINVAL;
+
+ index = (nsc->pg_offset + offset) >> AGP_PAGE_SHIFT;
+ nsc->gatt->ag_virtual[index] = 0;
+
+ return 0;
+}
+
+static void
+agp_nvidia_flush_tlb(struct agp_softc *sc)
+{
+ struct agp_nvidia_softc *nsc = sc->as_chipc;
+ u_int32_t wbc_reg;
+ volatile u_int32_t *ag_virtual;
+ int i, pages;
+
+ if (nsc->wbc_mask) {
+ wbc_reg = pci_conf_read(sc->as_pc, nsc->mc1_tag, AGP_NVIDIA_1_WBC);
+ wbc_reg |= nsc->wbc_mask;
+ pci_conf_write(sc->as_pc, nsc->mc1_tag, AGP_NVIDIA_1_WBC, wbc_reg);
+
+ /* Wait no more than 3 seconds. */
+ for (i = 0; i < 3000; i++) {
+ wbc_reg = pci_conf_read(sc->as_pc, nsc->mc1_tag, AGP_NVIDIA_1_WBC);
+ if ((nsc->wbc_mask & wbc_reg) == 0)
+ break;
+ else
+ DELAY(1000);
+ }
+ if (i == 3000)
+ aprint_debug_dev(sc->as_dev, "TLB flush took more than 3 seconds.\n");
+ }
+
+ ag_virtual = (volatile u_int32_t *)nsc->gatt->ag_virtual;
+
+ /* Flush TLB entries. */
+ pages = nsc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE;
+ for(i = 0; i < pages; i++)
+ (void)ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
+ for(i = 0; i < pages; i++)
+ (void)ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
+}
+
+#if 0
+static int
+agp_nvidia_detach(struct agp_softc *sc)
+{
+ struct agp_nvidia_softc *nsc = sc->as_chipc;
+ u_int32_t temp;
+
+ /* GART Control */
+ temp = pci_conf_read(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE);
+ pci_conf_write(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE, temp & ~(0x100));
+
+ /* GTLB Control */
+ temp = pci_conf_read(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL);
+ pci_conf_write(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11));
+
+ /* Put the aperture back the way it started. */
+ AGP_SET_APERTURE(sc, nsc->initial_aperture);
+
+ /* restore iorr for previous aperture size */
+ nvidia_init_iorr(AGP_GET_APERTURE(sc), nsc->initial_aperture);
+
+ pci_conf_write(sc->as_pc, nsc->mc2_tag, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11));
+
+ /* Put the aperture back the way it started. */
+ AGP_SET_APERTURE(sc, nsc->initial_aperture);
+
+ /* restore iorr for previous aperture size */
+ nvidia_init_iorr(AGP_GET_APERTURE(sc), nsc->initial_aperture);
+
+ agp_free_gatt(sc, nsc->gatt);
+
+ return 0;
+}
+#endif
+
+static int
+nvidia_init_iorr(u_int32_t addr, u_int32_t size)
+{
+ uint64_t base, mask, sys;
+ uint32_t iorr_addr, free_iorr_addr;
+
+ /* Find the iorr that is already used for the addr */
+ /* If not found, determine the uppermost available iorr */
+ free_iorr_addr = AMD_K7_NUM_IORR;
+ for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
+ base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
+ mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
+
+ if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
+ break;
+
+ if ((mask & 0x00000800ULL) == 0)
+ free_iorr_addr = iorr_addr;
+ }
+
+ if (iorr_addr >= AMD_K7_NUM_IORR) {
+ iorr_addr = free_iorr_addr;
+ if (iorr_addr >= AMD_K7_NUM_IORR)
+ return EINVAL;
+ }
+
+ base = (addr & ~0xfff) | 0x18;
+ mask = (0xfULL << 32) | rounddown2(0xfffff000, size) | 0x800;
+ wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
+ wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
+
+ sys = rdmsr(SYSCFG);
+ sys |= 0x00100000ULL;
+ wrmsr(SYSCFG, sys);
+
+ return 0;
+}
\ No newline at end of file
diff --git a/sys/dev/pci/agpreg.h b/sys/dev/pci/agpreg.h
index 647102d10cbd..6a73c87f7a27 100644
--- a/sys/dev/pci/agpreg.h
+++ b/sys/dev/pci/agpreg.h
@@ -319,6 +319,21 @@
#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
+/*
+ * NVIDIA nForce/nForce2 registers
+ */
+#define AGP_NVIDIA_0_APBASE 0x10
+#define AGP_NVIDIA_0_APSIZE 0x80
+#define AGP_NVIDIA_1_WBC 0xf0
+#define AGP_NVIDIA_2_GARTCTRL 0xd0
+#define AGP_NVIDIA_2_APBASE 0xd8
+#define AGP_NVIDIA_2_APLIMIT 0xdc
+#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
+#define AGP_NVIDIA_3_APBASE 0x50
+#define AGP_NVIDIA_3_APLIMIT 0x54
+#define AGP_NVIDIA_1_WBC 0xf0
+#define AGP_NVIDIA_NFORCE_WBC_MASK 0x00010000
+#define AGP_NVIDIA_NFORCE2_WBC_MASK 0x80000000
/*
* NVIDIA nForce3 registers
*/
diff --git a/sys/dev/pci/agpvar.h b/sys/dev/pci/agpvar.h
index e56a3bcf2009..177f3067cca6 100644
--- a/sys/dev/pci/agpvar.h
+++ b/sys/dev/pci/agpvar.h
@@ -190,8 +190,9 @@ int agp_amd_attach(device_t, device_t, void *);
int agp_apple_attach(device_t, device_t, void *);
int agp_i810_attach(device_t, device_t, void *);
int agp_intel_attach(device_t, device_t, void *);
-int agp_via_attach(device_t, device_t, void *);
int agp_sis_attach(device_t, device_t, void *);
+int agp_nvidia_attach(device_t, device_t, void *);
+int agp_via_attach(device_t, device_t, void *);
int agp_amd64_attach(device_t, device_t, void *);
int agp_alloc_dmamem(bus_dma_tag_t, size_t, int, bus_dmamap_t *, void **,
diff --git a/sys/dev/pci/files.agp b/sys/dev/pci/files.agp
index 5a23c0ff2ba0..c4199e070980 100644
--- a/sys/dev/pci/files.agp
+++ b/sys/dev/pci/files.agp
@@ -23,6 +23,9 @@ file dev/pci/agp_i810.c agp_i810 & agp needs-flag
define agp_intel
file dev/pci/agp_intel.c agp_intel & agp needs-flag
+define agp_nvidia
+file dev/pci/agp_nvidia.c agp_nvidia & agp needs-flag
+
define agp_sis
file dev/pci/agp_sis.c agp_sis & agp needs-flag
Home |
Main Index |
Thread Index |
Old Index