How does PCIe appear to the host?

[Mouse <mouse%Rodents-Montreal.ORG@localhost>]

How does PCIe differ from PCI from the CPU's point of view?  I'm
running into an issue and it seems to me this is important.

I've been having hardware (partially) fail on me recently, which is
breaking my backups.  In particular, I'm having trouble finding a
machine to connect the backup disks to - they're SATA, and I don't have
very many machines with SATA, and some of those SATA ports appear to be
broken (one machine, for example, has six, of which I've been able to
make only two work).

One of these machines is an ASRock Q1900M.  It has only two SATA ports
onboard; it has two PCIe x1 slots and a PCIe x16 slot.  I just today
picked up a 5-port PCIe SATA card and tried it.

The reason I'm asking about PCIe is that, as far as I can tell from the
host, it isn't there at all.  While this is a relatively old kernel,
I'd expect at least a "not configured" line - but dmesg is identical
between a boot with it and a boot without it.  So now I'm wondering
whether I've got a DOA card, or a duff slot, or I need to backport
something, or whether this is somehow expected, or what.

I've already backported the printout of PCIe capability in ppb.c.  The
ppbs report as

ppb0: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x1 @ 5.0GT/s
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
ppb1 at pci0 dev 28 function 1: vendor 0x8086 product 0x0f4a (rev. 0x0e)
ppb1: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x1 @ 5.0GT/s
pci2 at ppb1 bus 2
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
ppb2 at pci0 dev 28 function 2: vendor 0x8086 product 0x0f4c (rev. 0x0e)
ppb2: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x1 @ 5.0GT/s
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled, rd/line, wr/inv ok
ppb3 at pci0 dev 28 function 3: vendor 0x8086 product 0x0f4e (rev. 0x0e)
ppb3: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x1 @ 5.0GT/s

I note a possible conflict between the "x1" and the presence of a x16
slot; that 1 is coming from the PCIE_LCAP_MAX_WIDTH bits in PCIE_LCAP,
which makes me wonder whether something needs configuring to run the
x16 slot at more than x1.  The card does say it needs a x4 or higher
slot to work, so if the x16 slot is running x1 (is that even possible?)
that might be responsible.

Any thoughts?  Any pointers to where I might usefully look?

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