Re: CVS commit: src

[Paul Goyette <paul%whooppee.com@localhost>]

On Fri, 30 May 2008, Paul Goyette wrote:

> On Fri, 30 May 2008, Christoph Egger wrote:
>
> > The array termination needs to be fixed.
> > For AMD's L3 cache, 0 means it is disabled.
>
> I'll work on that!

Actually, this already works correctly.  The AMD L2 and L3 cache info 
tables both end with the entry

        __CI_TBL(0, 0x00,    0, 0, 0, NULL)

The cache_info_lookup() routine terminates its search when the cai_desc 
field is 0; cai_desc is the 2nd entry in the __CI_TBL macro.

So if a AMD cache is disabled the desc argument to cache_info_lookup() 
will be zero.  We'll search through the entire table until we reach the 
terminating entry, and then return (NULL).

Routine amd_cpu_cacheinfo() checks the return from cache_info_lookup() 
for NULL, and sets the cai->cai_associativity to 0.  When we get around 
to calling print_cache_config() we switch on the cai->cai_associativity 
and execute case 0 which prints "disabled".

I think the key here is that cache_info_lookup() matches its second 
argument (associativity value from cpuid) against the _second_ field in 
the table.  So for a disabled cache we search through the whole table 
and fall off the end, returning NULL.

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