[src/netbsd-8]: src/sys/arch/x86/x86 Pull up the following, requested by msai...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1ca689507276
branches:  netbsd-8
changeset: 936840:1ca689507276
user:      martin <martin%NetBSD.org@localhost>
date:      Wed Aug 05 17:27:48 2020 +0000

description:
Pull up the following, requested by msaitoh in ticket #1595:

        sys/arch/x86/include/specialreg.h               1.129 via patch
        sys/arch/x86/x86/errata.c                       1.24-1.26

- Add six errata for AMD Family 17h (Ryzen etc), tested by
  Patrick Welche and mrg@.

diffstat:

 sys/arch/x86/x86/errata.c |  84 ++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 79 insertions(+), 5 deletions(-)

diffs (126 lines):

diff -r 7e2ee796e66b -r 1ca689507276 sys/arch/x86/x86/errata.c
--- a/sys/arch/x86/x86/errata.c Wed Aug 05 17:22:45 2020 +0000
+++ b/sys/arch/x86/x86/errata.c Wed Aug 05 17:27:48 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: errata.c,v 1.23 2016/01/05 10:20:22 hannken Exp $      */
+/*     $NetBSD: errata.c,v 1.23.10.1 2020/08/05 17:27:48 martin Exp $  */
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -45,7 +45,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.23 2016/01/05 10:20:22 hannken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.23.10.1 2020/08/05 17:27:48 martin Exp $");
 
 #include <sys/types.h>
 #include <sys/systm.h>
@@ -70,8 +70,8 @@
        BH_E4, CH_CG, CH_D0, DH_CG, DH_D0, DH_E3, DH_E6, JH_E1,
        JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5,
        DR_BA, DR_B2, DR_B3, RB_C2, RB_C3, BL_C2, BL_C3, DA_C2,
-       DA_C3, HY_D0, HY_D1, HY_D1_G34R1,  PH_E0, LN_B0,
-       OINK
+       DA_C3, HY_D0, HY_D1, HY_D1_G34R1,  PH_E0, LN_B0, KB_A1,
+       ML_A1, ZP_B1, ZP_B2, PiR_B2, OINK
 } cpurev_t;
 
 static const u_int cpurevs[] = {
@@ -89,7 +89,9 @@
        RB_C2, 0x0100f42, RB_C3, 0x0100f43, BL_C2, 0x0100f52,
        BL_C3, 0x0100f53, DA_C2, 0x0100f62, DA_C3, 0x0100f63,
        HY_D0, 0x0100f80, HY_D1, 0x0100f81, HY_D1_G34R1, 0x0100f91,
-       PH_E0, 0x0100fa0, LN_B0, 0x0300f10,
+       PH_E0, 0x0100fa0, LN_B0, 0x0300f10, KB_A1, 0x0700F01,
+       ML_A1, 0x0730F01, ZP_B1, 0x0800F11, ZP_B2, 0x0800F12,
+       PiR_B2, 0x0800F82,
        OINK
 };
 
@@ -142,6 +144,22 @@
        DA_C3, HY_D0, HY_D1, HY_D1_G34R1,  PH_E0, LN_B0, OINK
 };
 
+static const uint8_t x86_errata_set12[] = {
+       KB_A1, OINK
+};
+
+static const uint8_t x86_errata_set13[] = {
+       ZP_B1, ZP_B2, PiR_B2, OINK
+};
+
+static const uint8_t x86_errata_set14[] = {
+       ZP_B1, OINK
+};
+
+static const uint8_t x86_errata_set15[] = {
+       KB_A1, ML_A1, OINK
+};
+
 static bool x86_errata_setmsr(struct cpu_info *, errata_t *);
 static bool x86_errata_testmsr(struct cpu_info *, errata_t *);
 
@@ -285,6 +303,62 @@
                721, FALSE, MSR_DE_CFG, x86_errata_set11,
                x86_errata_setmsr, DE_CFG_ERRATA_721
        },
+       /*
+        * 776: Incorrect Processor Branch Prediction for Two Consecutive
+        * Linear Pages
+        */
+       {
+               776, FALSE, MSR_IC_CFG, x86_errata_set12,
+               x86_errata_setmsr, IC_CFG_ERRATA_776
+       },
+       /*
+        * 793: Specific Combination of Writes to Write Combined Memory
+        * Types and Locked Instructions May Cause Core Hang
+        */
+       {
+               793, FALSE, MSR_LS_CFG, x86_errata_set15,
+               x86_errata_setmsr, LS_CFG_ERRATA_793
+       },
+       /*
+        * 1021: Load Operation May Receive Stale Data From Older Store
+        * Operation
+        */
+       {
+               1021, FALSE, MSR_DE_CFG, x86_errata_set13,
+               x86_errata_setmsr, DE_CFG_ERRATA_1021
+       },
+       /*
+        * 1033: A Lock Operation May Cause the System to Hang
+        */
+       {
+               1033, FALSE, MSR_LS_CFG, x86_errata_set14,
+               x86_errata_setmsr, LS_CFG_ERRATA_1033
+       },
+       /*
+        * 1049: FCMOV Instruction May Not Execute Correctly
+        */
+       {
+               1049, FALSE, MSR_FP_CFG, x86_errata_set13,
+               x86_errata_setmsr, FP_CFG_ERRATA_1049
+       },
+#if 0  /* Should we apply this errata? The other OSes don't. */
+       /*
+        * 1091: Address Boundary Crossing Load Operation May Receive
+        * Stale Data
+        */
+       {
+               1091, FALSE, MSR_LS_CFG2, x86_errata_set13,
+               x86_errata_setmsr, LS_CFG2_ERRATA_1091
+       },
+#endif
+       /*
+        * 1095: Potential Violation of Read Ordering In Lock Operation
+        * In SMT (Simultaneous Multithreading) Mode
+        */
+       {
+               1095, FALSE, MSR_LS_CFG, x86_errata_set13,
+               x86_errata_setmsr, LS_CFG_ERRATA_1095
+       },
 };
 
 static bool