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[src/netbsd-8]: src/sys/dev Pull up the following revisions, requested by msa...
details: https://anonhg.NetBSD.org/src/rev/7e2ee796e66b
branches: netbsd-8
changeset: 936839:7e2ee796e66b
user: martin <martin%NetBSD.org@localhost>
date: Wed Aug 05 17:22:45 2020 +0000
description:
Pull up the following revisions, requested by msaitoh in ticket #1594:
sys/dev/pci/if_wm.c 1.655-1.658, 1.660,
1.662, 1.664-1.668,
1.671-1.674, 1.678,
1.680-1.685 via patch
sys/dev/pci/if_wmreg.c 1.118-1.119 via patch
sys/dev/pci/if_wmvar.c 1.45 via patch
sys/dev/mii/igphy.c 1.35-1.36 via patch
sys/dev/mii/igphyreg.h 1.12-1.13
sys/dev/mii/makphy.c 1.66 via patch
sys/dev/mii/makphyreg.h 1.11
- Add SFP support. Module insertion/removal is not supported yet.
Currently, SFP detection is only done in the driver's attach phase.
- Detect the Media Auto Sense feature. Not supported yet.
- Fix SFF_SFP_ETH_FLAGS_100FX. It's not 0x10 but 0x20.
- Add extra delay in wm_serdes_power_up_link_82575().
- Add Intel I219 LM10-LM15 and V10-V14.
- wm(4) can use workqueue as deferred Rx/Tx handler).
Set hw.wm*.txrx_workqueue=1 to use workqueue instead of softint.
The default value of hw.wm*.txrx_workqueue is 0 which use softint
as before.
- Unset RSS UDP flags like ixg(4) and other OSes. To handle IP
fragmented UDP, first packet and second packet should be processed
in the same Rx queue.
- It's useless to not to set PCI_PMCSR_PME_STS bit when writing because
the bit is W1C. Instead, always write PCI_PMCSR_PME_STS bit to clear
in case it's already set.
- Actually writing always the checksum offload context descriptor
makes the HW do extra processing, avoid doing that if possible.
- Fix a bug that the WMREG_EEARBC_I210 register is incorrectly set if
the system uses iNVM.
- "wmX: 0" on 82542 is difficult to understand, so don't print it.
- Explicitly cast from uint16_t to uint32_t before shifting 16bit left
when printing Image Unique ID to avoid undefined behavior.
- Set if_baudrate for non-MII device.
- Rename some macros and function.
- KNF. Add comment.
diffstat:
sys/dev/mii/igphy.c | 38 +-
sys/dev/mii/igphyreg.h | 96 +++---
sys/dev/mii/makphy.c | 18 +-
sys/dev/mii/makphyreg.h | 28 +-
sys/dev/pci/if_wm.c | 655 +++++++++++++++++++++++++++++++++++++----------
sys/dev/pci/if_wmreg.h | 8 +-
sys/dev/pci/if_wmvar.h | 7 +-
7 files changed, 611 insertions(+), 239 deletions(-)
diffs (truncated from 1981 to 300 lines):
diff -r d5879bb7a174 -r 7e2ee796e66b sys/dev/mii/igphy.c
--- a/sys/dev/mii/igphy.c Wed Aug 05 16:20:08 2020 +0000
+++ b/sys/dev/mii/igphy.c Wed Aug 05 17:22:45 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: igphy.c,v 1.26.10.1 2017/08/01 23:33:18 snj Exp $ */
+/* $NetBSD: igphy.c,v 1.26.10.2 2020/08/05 17:22:46 martin Exp $ */
/*
* The Intel copyright applies to the analog register setup, and the
@@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.26.10.1 2017/08/01 23:33:18 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.26.10.2 2020/08/05 17:22:46 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_mii.h"
@@ -274,7 +274,7 @@
delay(20000);
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
PHY_WRITE(sc, 0x0000, 0x0140);
delay(5000);
@@ -282,7 +282,7 @@
for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)
IGPHY_WRITE(sc, code[i].reg, code[i].val);
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
PHY_WRITE(sc, 0x0000, 0x3300);
delay(20000);
@@ -327,9 +327,9 @@
}
if (igsc->sc_mactype == WM_T_82547) {
- fused = IGPHY_READ(sc, MII_IGPHY_ANALOG_SPARE_FUSE_STATUS);
+ fused = IGPHY_READ(sc, IGPHY_ANALOG_SPARE_FUSE_STATUS);
if ((fused & ANALOG_SPARE_FUSE_ENABLED) == 0) {
- fused = IGPHY_READ(sc, MII_IGPHY_ANALOG_FUSE_STATUS);
+ fused = IGPHY_READ(sc, IGPHY_ANALOG_FUSE_STATUS);
fine = fused & ANALOG_FUSE_FINE_MASK;
coarse = fused & ANALOG_FUSE_COARSE_MASK;
@@ -344,12 +344,12 @@
(fine & ANALOG_FUSE_FINE_MASK) |
(coarse & ANALOG_FUSE_COARSE_MASK);
- IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_CONTROL, fused);
- IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_BYPASS,
+ IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_CONTROL, fused);
+ IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_BYPASS,
ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
}
@@ -385,14 +385,14 @@
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
- reg = PHY_READ(sc, MII_IGPHY_PORT_CTRL);
+ reg = PHY_READ(sc, IGPHY_PORT_CTRL);
if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
reg |= PSCR_AUTO_MDIX;
reg &= ~PSCR_FORCE_MDI_MDIX;
- PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+ PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
} else {
reg &= ~(PSCR_AUTO_MDIX | PSCR_FORCE_MDI_MDIX);
- PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+ PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
}
mii_phy_setmedia(sc);
@@ -435,9 +435,9 @@
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
- pssr = PHY_READ(sc, MII_IGPHY_PORT_STATUS);
+ pssr = PHY_READ(sc, IGPHY_PORT_STATUS);
- if (pssr & PSSR_LINK_UP)
+ if (pssr & IGPHY_PSSR_LINK_UP)
mii->mii_media_status |= IFM_ACTIVE;
bmcr = PHY_READ(sc, MII_BMCR);
@@ -461,19 +461,19 @@
mii->mii_media_active |= IFM_NONE;
return;
}
- switch (pssr & PSSR_SPEED_MASK) {
- case PSSR_SPEED_1000MBPS:
+ switch (pssr & IGPHY_PSSR_SPEED_MASK) {
+ case IGPHY_PSSR_SPEED_1000MBPS:
mii->mii_media_active |= IFM_1000_T;
gtsr = PHY_READ(sc, MII_100T2SR);
if (gtsr & GTSR_MS_RES)
mii->mii_media_active |= IFM_ETH_MASTER;
break;
- case PSSR_SPEED_100MBPS:
+ case IGPHY_PSSR_SPEED_100MBPS:
mii->mii_media_active |= IFM_100_TX;
break;
- case PSSR_SPEED_10MBPS:
+ case IGPHY_PSSR_SPEED_10MBPS:
mii->mii_media_active |= IFM_10_T;
break;
@@ -483,7 +483,7 @@
return;
}
- if (pssr & PSSR_FULL_DUPLEX)
+ if (pssr & IGPHY_PSSR_FULL_DUPLEX)
mii->mii_media_active |=
IFM_FDX | mii_phy_flowstatus(sc);
else
diff -r d5879bb7a174 -r 7e2ee796e66b sys/dev/mii/igphyreg.h
--- a/sys/dev/mii/igphyreg.h Wed Aug 05 16:20:08 2020 +0000
+++ b/sys/dev/mii/igphyreg.h Wed Aug 05 17:22:45 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: igphyreg.h,v 1.10 2016/11/07 08:57:43 msaitoh Exp $ */
+/* $NetBSD: igphyreg.h,v 1.10.8.1 2020/08/05 17:22:46 martin Exp $ */
/*******************************************************************************
@@ -43,7 +43,7 @@
*/
/* IGP01E1000 Specific Port Config Register - R/W */
-#define MII_IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
+#define IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
#define PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define PSCFR_PRE_EN 0x0020
#define PSCFR_SMART_SPEED 0x0080
@@ -52,22 +52,22 @@
#define PSCFR_DISABLE_TRANSMIT 0x2000
/* IGP01E1000 Specific Port Status Register - R/O */
-#define MII_IGPHY_PORT_STATUS 0x11
-#define PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
-#define PSSR_POLARITY_REVERSED 0x0002
-#define PSSR_CABLE_LENGTH 0x007C
-#define PSSR_FULL_DUPLEX 0x0200
-#define PSSR_LINK_UP 0x0400
-#define PSSR_MDIX 0x0800
-#define PSSR_SPEED_MASK 0xC000 /* speed bits mask */
-#define PSSR_SPEED_10MBPS 0x4000
-#define PSSR_SPEED_100MBPS 0x8000
-#define PSSR_SPEED_1000MBPS 0xC000
-#define PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
-#define PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
+#define IGPHY_PORT_STATUS 0x11
+#define IGPHY_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
+#define IGPHY_PSSR_POLARITY_REVERSED 0x0002
+#define IGPHY_PSSR_CABLE_LENGTH 0x007C
+#define IGPHY_PSSR_FULL_DUPLEX 0x0200
+#define IGPHY_PSSR_LINK_UP 0x0400
+#define IGPHY_PSSR_MDIX 0x0800
+#define IGPHY_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
+#define IGPHY_PSSR_SPEED_10MBPS 0x4000
+#define IGPHY_PSSR_SPEED_100MBPS 0x8000
+#define IGPHY_PSSR_SPEED_1000MBPS 0xC000
+#define IGPHY_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
+#define IGPHY_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
/* IGP01E1000 Specific Port Control Register - R/W */
-#define MII_IGPHY_PORT_CTRL 0x12
+#define IGPHY_PORT_CTRL 0x12
#define PSCR_TP_LOOPBACK 0x0010
#define PSCR_CORRECT_NC_SCMBLR 0x0200
#define PSCR_TEN_CRS_SELECT 0x0400
@@ -76,7 +76,7 @@
#define PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
/* IGP01E1000 Specific Port Link Health Register */
-#define MII_IGPHY_LINK_HEALTH 0x13
+#define IGPHY_LINK_HEALTH 0x13
#define PLHR_VALID_CHANNEL_A 0x0001
#define PLHR_VALID_CHANNEL_B 0x0002
#define PLHR_VALID_CHANNEL_C 0x0004
@@ -96,61 +96,61 @@
#define GMII_SPD 0x20 /* Enable SPD */
/* IGP01E1000 Channel Quality Register */
-#define MII_IGPHY_CHANNEL_QUALITY 0x15
+#define IGPHY_CHANNEL_QUALITY 0x15
#define MSE_CHANNEL_A 0x000F
#define MSE_CHANNEL_B 0x00F0
#define MSE_CHANNEL_C 0x0F00
#define MSE_CHANNEL_D 0xF000
/* IGP01E1000 Power Management */
-#define MII_IGPHY_POWER_MGMT 0x19
+#define IGPHY_POWER_MGMT 0x19
#define PMR_SPD_EN 0x0001
#define PMR_D0_LPLU 0x0002
#define PMR_D3_LPLU 0x0004
#define PMR_DIS_1000 0x0040
-#define MII_IGPHY_PAGE_SELECT 0x1F
+#define IGPHY_PAGE_SELECT 0x1F
#define IGPHY_MAXREGADDR 0x1F
#define IGPHY_PAGEMASK (~IGPHY_MAXREGADDR)
/* IGP01E1000 AGC Registers - stores the cable length values*/
-#define MII_IGPHY_AGC_A 0x1172
-#define MII_IGPHY_AGC_PARAM_A 0x1171
-#define MII_IGPHY_AGC_B 0x1272
-#define MII_IGPHY_AGC_PARAM_B 0x1271
-#define MII_IGPHY_AGC_C 0x1472
-#define MII_IGPHY_AGC_PARAM_C 0x1471
-#define MII_IGPHY_AGC_D 0x1872
-#define MII_IGPHY_AGC_PARAM_D 0x1871
+#define IGPHY_AGC_A 0x1172
+#define IGPHY_AGC_PARAM_A 0x1171
+#define IGPHY_AGC_B 0x1272
+#define IGPHY_AGC_PARAM_B 0x1271
+#define IGPHY_AGC_C 0x1472
+#define IGPHY_AGC_PARAM_C 0x1471
+#define IGPHY_AGC_D 0x1872
+#define IGPHY_AGC_PARAM_D 0x1871
#define AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
#define AGC_LENGTH_TABLE_SIZE 128
#define AGC_RANGE 10
/* IGP01E1000 DSP Reset Register */
-#define MII_IGPHY_DSP_RESET 0x1F33
-#define MII_IGPHY_DSP_SET 0x1F71
-#define MII_IGPHY_DSP_FFE 0x1F35
-#define MII_IGPHY_CHANNEL_NUM 4
-#define MII_IGPHY_EDAC_MU_INDEX 0xC000
-#define MII_IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
-#define MII_IGPHY_ANALOG_TX_STATE 0x2890
-#define MII_IGPHY_ANALOG_CLASS_A 0x2000
-#define MII_IGPHY_FORCE_ANALOG_ENABLE 0x0004
-#define MII_IGPHY_DSP_FFE_CM_CP 0x0069
-#define MII_IGPHY_DSP_FFE_DEFAULT 0x002A
+#define IGPHY_DSP_RESET 0x1F33
+#define IGPHY_DSP_SET 0x1F71
+#define IGPHY_DSP_FFE 0x1F35
+#define IGPHY_CHANNEL_NUM 4
+#define IGPHY_EDAC_MU_INDEX 0xC000
+#define IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
+#define IGPHY_ANALOG_TX_STATE 0x2890
+#define IGPHY_ANALOG_CLASS_A 0x2000
+#define IGPHY_FORCE_ANALOG_ENABLE 0x0004
+#define IGPHY_DSP_FFE_CM_CP 0x0069
+#define IGPHY_DSP_FFE_DEFAULT 0x002A
/* IGP01E1000 PCS Initialization register - stores the polarity status */
-#define MII_IGPHY_PCS_INIT_REG 0x00B4
-#define MII_IGPHY_PCS_CTRL_REG 0x00B5
+#define IGPHY_PCS_INIT_REG 0x00B4
+#define IGPHY_PCS_CTRL_REG 0x00B5
-#define MII_IGPHY_ANALOG_REGS_PAGE 0x20C0
+#define IGPHY_ANALOG_REGS_PAGE 0x20C0
#define PHY_POLARITY_MASK 0x0078
/* IGP01E1000 Analog Register */
-#define MII_IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
-#define MII_IGPHY_ANALOG_FUSE_STATUS 0x20D0
-#define MII_IGPHY_ANALOG_FUSE_CONTROL 0x20DC
-#define MII_IGPHY_ANALOG_FUSE_BYPASS 0x20DE
+#define IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
+#define IGPHY_ANALOG_FUSE_STATUS 0x20D0
+#define IGPHY_ANALOG_FUSE_CONTROL 0x20DC
+#define IGPHY_ANALOG_FUSE_BYPASS 0x20DE
#define ANALOG_FUSE_POLY_MASK 0xF000
#define ANALOG_FUSE_FINE_MASK 0x0F80
#define ANALOG_FUSE_COARSE_MASK 0x0070
@@ -177,12 +177,12 @@
#define IGPHY_READ(sc, reg) \
- (PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, (reg) & ~0x1f), \
+ (PHY_WRITE(sc, IGPHY_PAGE_SELECT, (reg) & ~0x1f), \
PHY_READ(sc, (reg) & 0x1f))
#define IGPHY_WRITE(sc, reg, val) \
do { \
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, (reg) & ~0x1f); \
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, (reg) & ~0x1f); \
PHY_WRITE(sc, (reg) & 0x1f, val); \
} while (/*CONSTCOND*/0)
diff -r d5879bb7a174 -r 7e2ee796e66b sys/dev/mii/makphy.c
--- a/sys/dev/mii/makphy.c Wed Aug 05 16:20:08 2020 +0000
+++ b/sys/dev/mii/makphy.c Wed Aug 05 17:22:45 2020 +0000
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