[src/trunk]: src/sys/arch Add defines for MISC registers.

[kiyohara <kiyohara%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d2b28a6e7a52
branches:  trunk
changeset: 791479:d2b28a6e7a52
user:      kiyohara <kiyohara%NetBSD.org@localhost>
date:      Wed Nov 20 12:36:16 2013 +0000

description:
Add defines for MISC registers.

diffstat:

 sys/arch/arm/marvell/mvsocreg.h             |  42 +++++++++++++---------------
 sys/arch/evbarm/armadaxp/armadaxp_machdep.c |  10 +++---
 2 files changed, 25 insertions(+), 27 deletions(-)

diffs (119 lines):

diff -r 3aa9d31d1f4f -r d2b28a6e7a52 sys/arch/arm/marvell/mvsocreg.h
--- a/sys/arch/arm/marvell/mvsocreg.h   Wed Nov 20 12:29:13 2013 +0000
+++ b/sys/arch/arm/marvell/mvsocreg.h   Wed Nov 20 12:36:16 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsocreg.h,v 1.5 2013/09/30 13:15:46 kiyohara Exp $    */
+/*     $NetBSD: mvsocreg.h,v 1.6 2013/11/20 12:36:16 kiyohara Exp $    */
 /*
  * Copyright (c) 2007, 2008 KIYOHARA Takashi
  * All rights reserved.
@@ -56,12 +56,6 @@
 #define MVSOC_DSC_CSSR_SIZE_MASK       0xff000000
 
 /*
- * SoC MISC Register
- */
-
-#define MVSOC_MISC_BASE                (MVSOC_DEVBUS_BASE + 0x8200) /* For Armada XP */
-
-/*
  * Device Bus
  */
 #define MVSOC_DEVBUS_BASE      (UNITID2PHYS(DEVBUS))   /* 0x10000 */
@@ -69,19 +63,29 @@
 /*
  * General Purpose Port Registers
  */
-#define MVSOC_GPP_BASE                 (MVSOC_DEVBUS_BASE + 0x0100)
+#define MVSOC_GPP_BASE         (MVSOC_DEVBUS_BASE + 0x0100)
 
 /*
  * Two-Wire Serial Interface Registers
  */
-#define MVSOC_TWSI_BASE                        (MVSOC_DEVBUS_BASE + 0x1000)
+#define MVSOC_TWSI_BASE                (MVSOC_DEVBUS_BASE + 0x1000)
 
 /*
  * UART Interface Registers
  */
-                                       /* NS16550 compatible */
-#define MVSOC_COM0_BASE                        (MVSOC_DEVBUS_BASE + 0x2000)
-#define MVSOC_COM1_BASE                        (MVSOC_DEVBUS_BASE + 0x2100)
+                               /* NS16550 compatible */
+#define MVSOC_COM0_BASE                (MVSOC_DEVBUS_BASE + 0x2000)
+#define MVSOC_COM1_BASE                (MVSOC_DEVBUS_BASE + 0x2100)
+
+/*
+ * Miscellanseous Register
+ */
+#define MVSOC_MISC_BASE                (MVSOC_DEVBUS_BASE + 0x8200) /* For Armada XP */
+
+#define MVSOC_MISC_RSTOUTNMASKR                  0x60 /* RSTOUTn Mask Register */
+#define MVSOC_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN (1 << 0)
+#define MVSOC_MISC_SSRR                          0x64  /* System Soft Reset Register */
+#define MVSOC_MISC_SSRR_GLOBALSOFTRST           (1 << 0)
 
 /*
  * Mbus-L to Mbus Bridge Registers
@@ -108,17 +112,11 @@
 /* CPU Control and Status Registers */
 #define MVSOC_MLMB_CPUCR                 0x100 /* CPU Configuration Register */
 #define MVSOC_MLMB_CPUCSR                0x104 /* CPU Control/Status Register*/
-#if defined(ARMADAXP)
-#define MVSOC_MLMB_RSTOUTNMASKR                  0x60 /* RSTOUTn Mask Register */
-#define MVSOC_MLMB_SSRR                          0x64  /* System Soft Reset Register */
-#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN    (1 << 0)
-#else
 #define MVSOC_MLMB_RSTOUTNMASKR                  0x108 /* RSTOUTn Mask Register */
+#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN    (1 << 2)
+#define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN      (1 << 1)
+#define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN     (1 << 0)
 #define MVSOC_MLMB_SSRR                          0x10c /* System Soft Reset Register */
-#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN    (1 << 2)
-#endif
-#define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN     (1 << 0)
-#define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN      (1 << 1)
 #define MVSOC_MLMB_SSRR_SYSTEMSOFTRST           (1 << 0)
 #define MVSOC_MLMB_MLMBICR               0x110 /*Mb-L to Mb Bridge Intr Cause*/
 #define MVSOC_MLMB_MLMBIMR               0x114 /*Mb-L to Mb Bridge Intr Mask */
@@ -135,7 +133,7 @@
 /* CIB registers offsets */
 #define MVSOC_MLMB_CIB_CTRL_CFG                  0x280
 
-#define MVSOC_TMR_BASE                 (MVSOC_MLMB_BASE + 0x0300)
+#define MVSOC_TMR_BASE         (MVSOC_MLMB_BASE + 0x0300)
 
 /* CPU Doorbell Registers */
 #define MVSOC_MLMB_H2CDR                 0x400 /* Host-to-CPU Doorbell */
diff -r 3aa9d31d1f4f -r d2b28a6e7a52 sys/arch/evbarm/armadaxp/armadaxp_machdep.c
--- a/sys/arch/evbarm/armadaxp/armadaxp_machdep.c       Wed Nov 20 12:29:13 2013 +0000
+++ b/sys/arch/evbarm/armadaxp/armadaxp_machdep.c       Wed Nov 20 12:36:16 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armadaxp_machdep.c,v 1.3 2013/09/30 13:29:07 kiyohara Exp $    */
+/*     $NetBSD: armadaxp_machdep.c,v 1.4 2013/11/20 12:36:16 kiyohara Exp $    */
 /*******************************************************************************
 Copyright (C) Marvell International Ltd. and its affiliates
 
@@ -37,7 +37,7 @@
 *******************************************************************************/
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.3 2013/09/30 13:29:07 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.4 2013/11/20 12:36:16 kiyohara Exp $");
 
 #include "opt_machdep.h"
 #include "opt_mvsoc.h"
@@ -166,10 +166,10 @@
        cpu_reset_address = 0;
 
        /* Unmask soft reset */
-       write_miscreg(MVSOC_MLMB_RSTOUTNMASKR,
-           MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN);
+       write_miscreg(MVSOC_MISC_RSTOUTNMASKR,
+           MVSOC_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN);
        /* Assert soft reset */
-       write_miscreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST);
+       write_miscreg(MVSOC_MISC_SSRR, MVSOC_MISC_SSRR_GLOBALSOFTRST);
 
        while (1);
 }