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[src/trunk]: src/sys/arch/arm/marvell add ARMADA XP's Soc internal bus(Mbus) ...
details: https://anonhg.NetBSD.org/src/rev/9c201a317c21
branches: trunk
changeset: 808793:9c201a317c21
user: hsuenaga <hsuenaga%NetBSD.org@localhost>
date: Wed Jun 03 02:53:19 2015 +0000
description:
add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.
add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.
diffstat:
sys/arch/arm/marvell/armadaxp.c | 490 ++++++++++++++++++++++++++++++++++++-
sys/arch/arm/marvell/armadaxpreg.h | 143 +++++++++-
sys/arch/arm/marvell/armadaxpvar.h | 8 +-
3 files changed, 617 insertions(+), 24 deletions(-)
diffs (truncated from 836 to 300 lines):
diff -r aecbf168de2f -r 9c201a317c21 sys/arch/arm/marvell/armadaxp.c
--- a/sys/arch/arm/marvell/armadaxp.c Wed Jun 03 02:30:11 2015 +0000
+++ b/sys/arch/arm/marvell/armadaxp.c Wed Jun 03 02:53:19 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $");
#define _INTR_PRIVATE
@@ -97,10 +97,20 @@
static void armadaxp_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
static void armadaxp_pic_establish_irq(struct pic_softc *, struct intrsource *);
static void armadaxp_pic_set_priority(struct pic_softc *, int);
+static void armadaxp_pic_source_name(struct pic_softc *, int, char*, size_t);
static int armadaxp_find_pending_irqs(void);
static void armadaxp_pic_block_irq(struct pic_softc *, size_t);
+/* handle error cause */
+static void armadaxp_err_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void armadaxp_err_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static void armadaxp_err_pic_establish_irq(struct pic_softc *,
+ struct intrsource *);
+static void armadaxp_err_pic_source_name(struct pic_softc *,
+ int, char*, size_t);
+static int armadaxp_err_pic_pending_irqs(struct pic_softc *);
+
struct vco_freq_ratio {
uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
@@ -108,6 +118,303 @@
uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
};
+/*
+ * Interrupt names for ARMADA XP
+ */
+static const char * const armadaxp_pic_source_names[] = {
+ /* Main Interrupt Cause Per-CPU (IRQ 0-29) */
+ "InDBLowSum", "InDBHighSum", "OutDBSum", "CFU_LocalSum",
+ "SoC_ErrorSum", "LTimer0", "LTimer1", "LWDT", "GbE0_TH_RxTx",
+ "GbE0_RxTx", "GbE1_RxTxTh", "GbE1_RxTx", "GbE2_RxTxTh", "GbE2_RxTx",
+ "GbE3_RxTxTh", "GbE3_RxTx", "GPIO0_7", "GPIO8_15", "GPIO16_23",
+ "GPIO24_31", "GPIO32_39", "GPIO40_47", "GPIO48_55", "GPIO56_63",
+ "GPIO64_66", "SCNT", "PCNT", "Reserved27", "VCNT", "Reserved29",
+ /* Main Interrupt Cause Global-Shared (IRQ 30-115) */
+ "SPI0", "I2C0", "I2C1", "IDMA0", "IDMA1", "IDMA2", "IDMA3", "GTimer0",
+ "GTimer1", "GTimer2", "GTimer3", "UART0", "UART1", "UART2", "UART3",
+ "USB0", "USB1", "USB2", "CESA0", "CESA1", "RTC", "XOR0_Ch0",
+ "XOR0_Ch1", "BM", "SDIO", "SATA0", "TDM", "SATA1", "PEX0_0", "PEX0_1",
+ "PEX0_2", "PEX0_3", "PEX1_0", "PEX1_1", "PEX1_2", "PEX1_3",
+ "GbE0_Sum", "GbE0_Rx", "GbE0_Tx", "GbE0_Misc", "GbE1_Sum", "GbE1_Rx",
+ "GbE1_Tx", "GbE1_Misc", "GbE2_Sum", "GbE2_Rx", "GbE2_Tx", "GbE2_Misc",
+ "GbE3_Sum", "GbE3_Rx", "GbE3_Tx", "GbE3_Misc", "GPIO0_7", "GPIO8_15",
+ "GPIO16_23", "GPIO24_31", "Reserved86", "GPIO32_39", "GPIO40_47",
+ "GPIO48_55", "GPIO56_63", "GPIO64_66", "SPI1", "WDT", "XOR1_Ch2",
+ "XOR1_Ch3", "SharedDB1Sum", "SharedDB2Sum", "SharedDB3Sum", "PEX2_0",
+ "Reserved100", "Reserved101", "Reserved102", "PEX3_0", "Reserved104",
+ "Reserved105", "Reserved106", "PMU", "DRAM", "GbE0_Wakeup",
+ "GbE1_Wakeup", "GbE2_Wakeup", "GbE3_Wakeup", "NAND", "Reserved114",
+ "Reserved115"
+};
+static const char * const armadaxp_err_pic_source_names[] = {
+ /*
+ * IRQ 120-151 (bit 0-31 in SoC Error Interrupt Cause register)
+ * connected to SoC_ErrorSum in Main Interrupt Cause
+ */
+ "ERR_CESA0", "ERR_DevBus", "ERR_IDMA", "ERR_XOR1",
+ "ERR_PEX0", "ERR_PEX1", "ERR_GbE", "ERR_CESA1",
+ "ERR_USB", "ERR_DRAM", "ERR_XOR0", "ERR_Reserved11",
+ "ERR_BM", "ERR_CIB", "ERR_Reserved14", "ERR_PEX2",
+ "ERR_PEX3", "ERR_SATA0", "ERR_SATA1", "ERR_Reserved19",
+ "ERR_TDM", "ERR_NAND", "ERR_Reserved22",
+ "ERR_Reserved23", "ERR_Reserved24", "ERR_Reserved25",
+ "ERR_Reserved26", "ERR_Reserved27", "ERR_Reserved28",
+ "ERR_Reserved29", "ERR_Reserved30", "ERR_Reserved31",
+};
+
+/*
+ * Mbus Target and Attribute bindings for ARMADA XP
+ */
+static struct mbus_description {
+ uint8_t target;
+ uint8_t attr;
+ const char *string;
+} mbus_desc[] = {
+ /* DDR */
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS0,
+ "DDR(M_CS[0])" },
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS1,
+ "DDR(M_CS[1])" },
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS2,
+ "DDR(M_CS[2])" },
+ { ARMADAXP_UNITID_DDR, ARMADAXP_ATTR_DDR_CS3,
+ "DDR(M_CS[3])" },
+
+ /* DEVBUS */
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS0,
+ "DEVBUS(SPI0 CS0)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS1,
+ "DEVBUS(SPI0 CS1)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS2,
+ "DEVBUS(SPI0 CS2)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS3,
+ "DEVBUS(SPI0 CS3)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS4,
+ "DEVBUS(SPI0 CS4)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS5,
+ "DEVBUS(SPI0 CS5)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS6,
+ "DEVBUS(SPI0 CS6)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI0_CS7,
+ "DEVBUS(SPI0 CS7)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS0,
+ "DEVBUS(SPI1 CS0)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS1,
+ "DEVBUS(SPI1 CS1)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS2,
+ "DEVBUS(SPI1 CS2)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS3,
+ "DEVBUS(SPI1 CS3)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS4,
+ "DEVBUS(SPI1 CS4)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS5,
+ "DEVBUS(SPI1 CS5)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS6,
+ "DEVBUS(SPI1 CS6)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_SPI1_CS7,
+ "DEVBUS(SPI1 CS7)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS0,
+ "DEVBUS(DevCS[0])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS1,
+ "DEVBUS(DevCS[1])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS2,
+ "DEVBUS(DevCS[2])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS3,
+ "DEVBUS(DevCS[3])" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_CS,
+ "DEVBUS(BootCS)" },
+ { ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_ROM,
+ "DEVBUS(BootROM)" },
+
+ /* GbE */
+ { ARMADAXP_UNITID_GBE0, ARMADAXP_ATTR_GBE_RESERVED,
+ "GBE0 GBE1" },
+ { ARMADAXP_UNITID_GBE2, ARMADAXP_ATTR_GBE_RESERVED,
+ "GBE2 GBE3" },
+
+ /* PEX(PCIe) */
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_MEM,
+ "PEX0(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx1_MEM,
+ "PEX0(Lane1, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx2_MEM,
+ "PEX0(Lane2, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx3_MEM,
+ "PEX0(Lane3, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEX2_MEM,
+ "PEX2(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx0_MEM,
+ "PEX1(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx1_MEM,
+ "PEX1(Lane1, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx2_MEM,
+ "PEX1(Lane2, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx3_MEM,
+ "PEX1(Lane3, Memory)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEX2_MEM,
+ "PEX3(Lane0, Memory)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_IO,
+ "PEX0(Lane0, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx1_IO,
+ "PEX0(Lane1, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx2_IO,
+ "PEX0(Lane2, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx3_IO,
+ "PEX0(Lane3, I/O)" },
+ { ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEX2_IO,
+ "PEX2(Lane0, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx0_IO,
+ "PEX1(Lane0, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx1_IO,
+ "PEX1(Lane1, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx2_IO,
+ "PEX1(Lane2, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx3_IO,
+ "PEX1(Lane3, I/O)" },
+ { ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEX2_IO,
+ "PEX3(Lane0, I/O)" },
+
+ /* CRYPT */
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_NOSWAP,
+ "CESA0(No swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_SWAP_BYTE,
+ "CESA0(Byte swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_SWAP_BYTE_WORD,
+ "CESA0(Byte and word swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_SWAP_WORD,
+ "CESA0(Word swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_NOSWAP,
+ "CESA1(No swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_SWAP_BYTE,
+ "CESA1(Byte swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_SWAP_BYTE_WORD,
+ "CESA1(Byte and word swap)" },
+ { ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT1_SWAP_WORD,
+ "CESA1(Word swap)" },
+
+ /* BM */
+ { ARMADAXP_UNITID_BM, ARMADAXP_ATTR_BM_RESERVED,
+ "BM" },
+
+ /* NAND */
+ { ARMADAXP_UNITID_NAND, ARMADAXP_ATTR_NAND_RESERVED,
+ "NAND" },
+};
+
+/*
+ * Default Mbus addrss decoding table for ARMADA XP
+ * this table may changed by device drivers.
+ *
+ * NOTE: some version of u-boot is broken. it writes old decoding table.
+ * probably, it's designed for Kirkwood SoC or older. we need to restore
+ * ARMADA XP's parameter set.
+ */
+static struct mbus_table_def {
+ int window; /* index of address decoding window registers */
+ uint32_t base; /* base address of the window */
+ uint32_t size; /* size of the window */
+ uint8_t target; /* target unit of the window */
+ uint8_t attr; /* target attribute of the window */
+} mbus_table[] = {
+ /*
+ * based on 'default address mapping' described in Marvell's document
+ * 'ARMADA XP Functional Specifications.'
+ *
+ * some windows are modified to get compatibility with old codes.
+ */
+ {
+ /* PCIe 0 lane0 MEM */
+ /* MODIFIED (moved to MARVELL_PEXMEM_PBASE) */
+ 0, 0xe0000000, 0x01000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx0_MEM
+ },
+ {
+ /* PCIe 0 lane1 MEM */
+ 1, 0x88000000, 0x08000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx1_MEM
+ },
+ {
+ /* PCIe 0 lane2 MEM */
+ 2, 0x90000000, 0x08000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx2_MEM
+ },
+ {
+ /* PCIe 0 lane3 MEM */
+ 3, 0x98000000, 0x08000000,
+ ARMADAXP_UNITID_PEX0, ARMADAXP_ATTR_PEXx3_MEM
+ },
+ {
+ /* PCIe 1 lane0 MEM */
+ 4, 0xa0000000, 0x08000000,
+ ARMADAXP_UNITID_PEX1, ARMADAXP_ATTR_PEXx0_MEM
+ },
+ { 5, 0, 0, 0, 0 /* disabled */ },
+ { 6, 0, 0, 0, 0 /* disabled */ },
+ { 7, 0, 0, 0, 0 /* disabled */ },
+ {
+ /* Security Accelerator SRAM, Engine 0, no data swap */
+ 8, 0xc8010000, 0x00010000,
+ ARMADAXP_UNITID_CRYPT, ARMADAXP_ATTR_CRYPT0_NOSWAP,
+ },
+ {
+ /* Device bus, BOOT_CS */
+ 9, 0xd8000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_BOOT_CS,
+ },
+ {
+ /* Device bus, DEV_CS[0] */
+ /* MODIFIED (moved, conflict to MARVELL_PEXMEM_PBASE here.) */
+ 10, 0x80000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS0
+ },
+ {
+ /* Device bus, DEV_CS[1] */
+ 11, 0xe8000000, 0x08000000,
+ ARMADAXP_UNITID_DEVBUS, ARMADAXP_ATTR_DEVBUS_DEV_CS1
+ },
+ {
+ /* Device bus, DEV_CS[2] */
+ /* MODIFIED: (disabled, conflict to MARVELL_PEXIO_PBASE) */
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