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[src/netbsd-6]: src/usr.sbin/cpuctl Pull up following revision(s) (requested ...
details: https://anonhg.NetBSD.org/src/rev/466aa63da4d7
branches: netbsd-6
changeset: 776866:466aa63da4d7
user: snj <snj%NetBSD.org@localhost>
date: Fri Jan 16 08:30:50 2015 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
diffstat:
usr.sbin/cpuctl/arch/i386-asm.S | 57 +-
usr.sbin/cpuctl/arch/i386.c | 2056 ++++++++++++++++++++----------------
usr.sbin/cpuctl/arch/x86_64-asm.S | 20 +-
usr.sbin/cpuctl/cpuctl.8 | 13 +-
usr.sbin/cpuctl/cpuctl.c | 28 +-
usr.sbin/cpuctl/cpuctl.h | 4 +-
6 files changed, 1181 insertions(+), 997 deletions(-)
diffs (truncated from 2876 to 300 lines):
diff -r f589fc84c089 -r 466aa63da4d7 usr.sbin/cpuctl/arch/i386-asm.S
--- a/usr.sbin/cpuctl/arch/i386-asm.S Fri Jan 16 08:22:25 2015 +0000
+++ b/usr.sbin/cpuctl/arch/i386-asm.S Fri Jan 16 08:30:50 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i386-asm.S,v 1.1 2008/05/05 17:54:14 ad Exp $ */
+/* $NetBSD: i386-asm.S,v 1.1.24.1 2015/01/16 08:30:50 snj Exp $ */
/*-
* Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@@ -30,15 +30,6 @@
#include <machine/cputypes.h>
#include <machine/psl.h>
- .data
-
-_C_LABEL(cpu):
- .long 0
- .globl _C_LABEL(cpu)
-_C_LABEL(cpu_info_level):
- .long -1
- .globl _C_LABEL(cpu_info_level)
-
.text
ENTRY(x86_cpuid2)
@@ -57,8 +48,12 @@
ret
END(x86_cpuid2)
+ENTRY(x86_xgetbv)
+ xgetbv
+ ret
+END(x86_xgetbv)
+
ENTRY(x86_identify)
- pushl %ebx
/* Try to toggle alignment check flag; does not exist on 386. */
pushfl
popl %eax
@@ -91,11 +86,11 @@
* Don't try cpuid, as Nx586s reportedly don't support the
* PSL_ID bit.
*/
- movl $CPU_NX586,_C_LABEL(cpu)
- jmp 2f
+ movl $CPU_NX586,%eax
+ ret
is386:
- movl $CPU_386,_C_LABEL(cpu)
- jmp 2f
+ movl $CPU_386,%eax
+ ret
try486: /* Try to toggle identification flag; does not exist on early 486s. */
pushfl
@@ -112,8 +107,13 @@
popfl
testl %eax,%eax
- jnz try586
-is486: movl $CPU_486,_C_LABEL(cpu)
+ jz is486
+
+ /* Later cpu, caller will use cpuid instruction */
+ movl $-1,%eax
+ ret
+
+is486:
/*
* Check Cyrix CPU
* Cyrix CPUs do not change the undefined flags following
@@ -129,9 +129,11 @@
divl %ecx
jnc trycyrix486
popfl
- jmp 2f
+ movl $CPU_486,%eax
+ ret
+
trycyrix486:
- movl $CPU_6x86,_C_LABEL(cpu) # set CPU type
+ popfl
/*
* Check for Cyrix 486 CPU by seeing if the flags change during a
* divide. This is documented in the Cx486SLC/e SMM Programmer's
@@ -139,6 +141,7 @@
*/
xorl %edx,%edx
cmpl %edx,%edx # set flags to known state
+ pushl %ebx
pushfl
popl %ecx # store flags in ecx
movl $-1,%eax
@@ -146,15 +149,13 @@
divl %ebx # do a long division
pushfl
popl %eax
+ popl %ebx
xorl %ecx,%eax # are the flags different?
testl $0x8d5,%eax # only check C|PF|AF|Z|N|V
- jne 2f # yes; must be Cyrix 6x86 CPU
- movl $CPU_486DLC,_C_LABEL(cpu)# set CPU type
- jmp 2f
-try586: /* Use the `cpuid' instruction. */
- xorl %eax,%eax
- cpuid
- movl %eax,_C_LABEL(cpu_info_level)
-2:
- popl %ebx
+ je is486dlc # yes => must be Cyrix 6x86 CPU
+ movl $CPU_6x86,%eax
ret
+
+is486dlc:
+ movl $CPU_486DLC,%eax
+ ret
diff -r f589fc84c089 -r 466aa63da4d7 usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c Fri Jan 16 08:22:25 2015 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c Fri Jan 16 08:30:50 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.27.2.4 2012/04/19 20:04:37 riz Exp $ */
+/* $NetBSD: i386.c,v 1.27.2.5 2015/01/16 08:30:50 snj Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.27.2.4 2012/04/19 20:04:37 riz Exp $");
+__RCSID("$NetBSD: i386.c,v 1.27.2.5 2015/01/16 08:30:50 snj Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -81,25 +81,27 @@
#include <x86/cacheinfo.h>
#include "../cpuctl.h"
+#include "cpuctl_i386.h"
/* Size of buffer for printing humanized numbers */
#define HUMAN_BUFSIZE sizeof("999KB")
-#define x86_cpuid(a,b) x86_cpuid2((a),0,(b))
-
-void x86_cpuid2(uint32_t, uint32_t, uint32_t *);
-void x86_identify(void);
-
struct cpu_info {
const char *ci_dev;
- int32_t ci_cpuid_level;
+ int32_t ci_cpu_type; /* for cpu's without cpuid */
+ int32_t ci_cpuid_level; /* highest cpuid supported */
+ uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */
uint32_t ci_signature; /* X86 cpuid type */
- uint32_t ci_feat_val[5]; /* X86 CPUID feature bits
+ uint32_t ci_family; /* from ci_signature */
+ uint32_t ci_model; /* from ci_signature */
+ uint32_t ci_feat_val[8]; /* X86 CPUID feature bits
* [0] basic features %edx
* [1] basic features %ecx
* [2] extended features %edx
* [3] extended features %ecx
* [4] VIA padlock features
+ * [5] XCR0 bits (d:0 %eax)
+ * [6] xsave flags (d:1 %eax)
*/
uint32_t ci_cpu_class; /* CPU class */
uint32_t ci_brand_id; /* Intel brand id */
@@ -110,6 +112,10 @@
uint8_t ci_coreid;
uint8_t ci_smtid;
uint32_t ci_initapicid;
+
+ uint32_t ci_cur_xsave;
+ uint32_t ci_max_xsave;
+
struct x86_cache_info ci_cinfo[CAI_COUNT];
void (*ci_info)(struct cpu_info *);
};
@@ -124,22 +130,17 @@
void (*cpu_info)(struct cpu_info *);
};
-struct cpu_extend_nameclass {
- int ext_model;
- const char *cpu_models[CPU_MAXMODEL+1];
-};
-
struct cpu_cpuid_nameclass {
const char *cpu_id;
int cpu_vendor;
const char *cpu_vendorname;
struct cpu_cpuid_family {
int cpu_class;
- const char *cpu_models[CPU_MAXMODEL+2];
+ const char *cpu_models[256];
+ const char *cpu_model_default;
void (*cpu_setup)(struct cpu_info *);
void (*cpu_probe)(struct cpu_info *);
void (*cpu_info)(struct cpu_info *);
- struct cpu_extend_nameclass *cpu_extended_names;
} cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1];
};
@@ -147,7 +148,9 @@
/*
* Map Brand ID from cpuid instruction to brand name.
- * Source: Intel Processor Identification and the CPUID Instruction, AP-485
+ * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32
+ * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32
+ * Architectures Software Developer's Manual, Volume 2A".
*/
static const char * const i386_intel_brand[] = {
"", /* Unsupported */
@@ -155,7 +158,7 @@
"Pentium III", /* Intel (R) Pentium (R) III processor */
"Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */
"Pentium III", /* Intel (R) Pentium (R) III processor */
- "", /* Reserved */
+ "", /* 0x05: Reserved */
"Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */
"Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
@@ -163,9 +166,17 @@
"Celeron", /* Intel (R) Celeron (TM) processor */
"Xeon", /* Intel (R) Xeon (TM) processor */
"Xeon MP", /* Intel (R) Xeon (TM) processor MP */
- "", /* Reserved */
+ "", /* 0x0d: Reserved */
"Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */
"Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
+ "", /* 0x10: Reserved */
+ "Mobile Genuine", /* Moblie Genuine Intel (R) processor */
+ "Celeron M", /* Intel (R) Celeron (R) M processor */
+ "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
+ "Celeron", /* Intel (R) Celeron (R) processor */
+ "Mobile Genuine", /* Moblie Genuine Intel (R) processor */
+ "Pentium M", /* Intel (R) Pentium (R) M processor */
+ "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
};
/*
@@ -184,31 +195,38 @@
static char amd_brand_name[48];
static int use_pae, largepagesize;
-static void via_cpu_probe(struct cpu_info *);
-static void amd_family6_probe(struct cpu_info *);
-static void intel_family_new_probe(struct cpu_info *);
+/* Setup functions */
+static void disable_tsc(struct cpu_info *);
+static void amd_family5_setup(struct cpu_info *);
+static void cyrix6x86_cpu_setup(struct cpu_info *);
+static void winchip_cpu_setup(struct cpu_info *);
+/* Brand/Model name functions */
static const char *intel_family6_name(struct cpu_info *);
static const char *amd_amd64_name(struct cpu_info *);
-static void amd_family5_setup(struct cpu_info *);
-static void transmeta_cpu_info(struct cpu_info *);
+/* Probe functions */
+static void amd_family6_probe(struct cpu_info *);
+static void powernow_probe(struct cpu_info *);
+static void intel_family_new_probe(struct cpu_info *);
+static void via_cpu_probe(struct cpu_info *);
+/* (Cache) Info functions */
+static void intel_cpu_cacheinfo(struct cpu_info *);
+static void amd_cpu_cacheinfo(struct cpu_info *);
+static void via_cpu_cacheinfo(struct cpu_info *);
+static void tmx86_get_longrun_status(u_int *, u_int *, u_int *);
+static void transmeta_cpu_info(struct cpu_info *);
+/* Common functions */
+static void cpu_probe_base_features(struct cpu_info *, const char *);
+static void cpu_probe_hv_features(struct cpu_info *, const char *);
+static void cpu_probe_features(struct cpu_info *);
+static void print_bits(const char *, const char *, const char *, uint32_t);
+static void identifycpu_cpuids(struct cpu_info *);
+static const struct x86_cache_info *cache_info_lookup(
+ const struct x86_cache_info *, uint8_t);
static const char *print_cache_config(struct cpu_info *, int, const char *,
const char *);
static const char *print_tlb_config(struct cpu_info *, int, const char *,
const char *);
-static void amd_cpu_cacheinfo(struct cpu_info *);
-static void via_cpu_cacheinfo(struct cpu_info *);
-static void x86_print_cacheinfo(struct cpu_info *);
-static const struct x86_cache_info *cache_info_lookup(
- const struct x86_cache_info *, uint8_t);
-static void cyrix6x86_cpu_setup(struct cpu_info *);
-static void winchip_cpu_setup(struct cpu_info *);
-static void amd_family5_setup(struct cpu_info *);
-static void powernow_probe(struct cpu_info *);
-
-/*
- * Info for CTL_HW
- */
-static char cpu_model[120];
+static void x86_print_cache_and_tlb_info(struct cpu_info *);
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