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[src/nathanw_sa]: src/sys/arch/mips/alchemy Add support for the the Alchemy S...
details: https://anonhg.NetBSD.org/src/rev/f7d41735f11a
branches: nathanw_sa
changeset: 506070:f7d41735f11a
user: simonb <simonb%NetBSD.org@localhost>
date: Mon Jul 29 15:39:12 2002 +0000
description:
Add support for the the Alchemy Semiconductor Au1x00 series on-chip
devices. Currently the serial ports and ethernet MAC have working
drivers, and this has only been physically tested on the Au1000 CPU,
but these devices should work on the Au1100 and Au1500 CPUs too.
diffstat:
sys/arch/mips/alchemy/au_cpureg_mem.c | 59 ++++++++++
sys/arch/mips/alchemy/au_timer.c | 146 +++++++++++++++++++++++++
sys/arch/mips/alchemy/dev/if_aumacreg.h | 176 +++++++++++++++++++++++++++++++
sys/arch/mips/alchemy/include/aubusvar.h | 25 ++++
sys/arch/mips/alchemy/include/auvar.h | 58 ++++++++++
5 files changed, 464 insertions(+), 0 deletions(-)
diffs (truncated from 484 to 300 lines):
diff -r 8ca0c3a50822 -r f7d41735f11a sys/arch/mips/alchemy/au_cpureg_mem.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/au_cpureg_mem.c Mon Jul 29 15:39:12 2002 +0000
@@ -0,0 +1,59 @@
+/* $NetBSD: au_cpureg_mem.c,v 1.1.2.2 2002/07/29 15:39:12 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Platform-specific SOC register support for the Alchemy Semiconductor Au1X00.
+ */
+
+#include <sys/param.h>
+
+#include <machine/bus.h>
+#include <mips/alchemy/include/auvar.h>
+#include <mips/alchemy/include/aubusvar.h>
+
+#define CHIP au_cpureg
+#define CHIP_MEM /* defined */
+#define CHIP_ACCESSTYPE uint32_t
+
+/* MEM region 1 */
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0x1fffffffUL
+#define CHIP_W1_SYS_START(v) 0UL
+#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
diff -r 8ca0c3a50822 -r f7d41735f11a sys/arch/mips/alchemy/au_timer.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/au_timer.c Mon Jul 29 15:39:12 2002 +0000
@@ -0,0 +1,146 @@
+/* $NetBSD: au_timer.c,v 1.1.2.2 2002/07/29 15:39:13 simonb Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+
+#include <machine/bus.h>
+#include <mips/locore.h>
+
+#include <evbmips/evbmips/clockvar.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+/*
+ * Set a programmable clock register.
+ * If "wait" is non-zero, wait for that bit to become 0 in the
+ * counter control register before and after writing to the
+ * specified clock register.
+ */
+#define SET_PC_REG(reg, wait, val) \
+do { \
+ if (wait) \
+ while (bus_space_read_4(st, sh, PC_COUNTER_CONTROL) \
+ & (wait)) \
+ /* nothing */; \
+ bus_space_write_4(st, sh, (reg), (val)); \
+ if (wait) \
+ while (bus_space_read_4(st, sh, (reg)) & (wait)) \
+ /* nothing */; \
+} while (0)
+
+void
+au_cal_timers(bus_space_tag_t st, bus_space_handle_t sh)
+{
+ uint32_t ctrdiff[4], startctr, endctr;
+ uint32_t ctl, ctr, octr;
+ int i;
+
+ /* Enable the programmable counter 1. */
+ ctl = bus_space_read_4(st, sh, PC_COUNTER_CONTROL);
+ if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1));
+ SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl | CC_EO | CC_EN1);
+
+ /* Initialize for 16Hz. */
+ SET_PC_REG(PC_TRIM1, CC_T1S, PC_RATE / 16 - 1);
+
+ /* Run the loop an extra time to prime the cache. */
+ for (i = 0; i < 4; i++) {
+ /* Reset the counter. */
+ SET_PC_REG(PC_COUNTER_WRITE1, CC_C1S, 0);
+
+ /* Wait for 1/16th of a second. */
+ //startctr = mips3_cp0_count_read();
+
+ /* Wait for the PC to tick over. */
+ ctr = bus_space_read_4(st, sh, PC_COUNTER_READ_1);
+ do {
+ octr = bus_space_read_4(st, sh, PC_COUNTER_READ_1);
+ } while (ctr == octr);
+
+ startctr = mips3_cp0_count_read();
+ do {
+ ctr = bus_space_read_4(st, sh, PC_COUNTER_READ_1);
+ } while (ctr == octr); // while (ctr <= octr + 1);
+ endctr = mips3_cp0_count_read();
+ ctrdiff[i] = endctr - startctr;
+ }
+
+ /* Disable the counter (if it wasn't enabled already). */
+ if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1));
+ SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl);
+
+ /* Compute the number of cycles per second. */
+ curcpu()->ci_cpu_freq = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16;
+
+ /* Compute the number of ticks for hz. */
+ curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
+
+ /* Compute the delay divisor. */
+ curcpu()->ci_divisor_delay =
+ ((curcpu()->ci_cpu_freq + 500000) / 1000000);
+
+ /*
+ * To implement a more accurate microtime using the CP0 COUNT
+ * register we need to divide that register by the number of
+ * cycles per MHz. But...
+ *
+ * DIV and DIVU are expensive on MIPS (eg 75 clocks on the
+ * R4000). MULT and MULTU are only 12 clocks on the same CPU.
+ * On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
+ * clocks for MUL/MULTU.
+ *
+ * The strategy we use to to calculate the reciprical of cycles
+ * per MHz, scaled by 1<<32. Then we can simply issue a MULTU
+ * and pluck of the HI register and have the results of the
+ * division.
+ */
+ curcpu()->ci_divisor_recip =
+ 0x100000000ULL / curcpu()->ci_divisor_delay;
+
+ /*
+ * Get correct cpu frequency if the CPU runs at twice the
+ * external/cp0-count frequency.
+ */
+ if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+ curcpu()->ci_cpu_freq *= 2;
+
+#ifdef DEBUG
+ printf("Timer calibration: %lu cycles/sec [(%u, %u) * 16]\n",
+ curcpu()->ci_cpu_freq, ctrdiff[2], ctrdiff[3]);
+#endif
+}
diff -r 8ca0c3a50822 -r f7d41735f11a sys/arch/mips/alchemy/dev/if_aumacreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/dev/if_aumacreg.h Mon Jul 29 15:39:12 2002 +0000
@@ -0,0 +1,176 @@
+/* $NetBSD: if_aumacreg.h,v 1.1.2.2 2002/07/29 15:39:15 simonb Exp $ */
+
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MIPS_ALCHEMY_DEV_AUMACREG_H_
+#define _MIPS_ALCHEMY_DEV_AUMACREG_H_
+
+/*
+ * Register description for the Alchemy Semiconductor Au1X00
+ * Ethernet Media Access Controllers.
+ */
+
+#define MAC_BUFLEN 0x0800
+#define MAC_BUFLEN_JUMBO 0x2800
+
+/*
+ * MAC registers.
+ */
+
+#define MAC_CONTROL 0x0000 /* MAC control */
+#define CONTROL_RA (1U << 31) /* receive all */
+#define CONTROL_EM (1U << 30) /* 1 = big endian */
+#define CONTROL_DO (1U << 23) /* disable receive own */
+#define CONTROL_LM(x) ((x) << 21) /* loopback mode */
+ /* 0 = normal */
+ /* 1 = internal loopback */
+ /* 2 = external loopback */
+ /* 3 = reserved */
+#define CONTROL_F (1U << 20) /* full-duplex mode */
+#define CONTROL_PM (1U << 19) /* pass all multicast */
+#define CONTROL_PR (1U << 18) /* promiscuous mode */
+#define CONTROL_IF (1U << 17) /* inverse filtering */
+#define CONTROL_PB (1U << 16) /* pass bad frames */
+#define CONTROL_HO (1U << 15) /* hash-only filtering */
+#define CONTROL_HP (1U << 13) /* hash-perfect filtering */
+#define CONTROL_LC (1U << 12) /* re-tx on late collision */
+#define CONTROL_DB (1U << 11) /* disable broadcast frames */
+#define CONTROL_DR (1U << 10) /* disable retry */
+#define CONTROL_AP (1U << 8) /* automatic pad stripping */
+#define CONTROL_BL(x) ((x) << 6) /* backoff limit */
+#define CONTROL_DC (1U << 5) /* deferral check */
+#define CONTROL_TE (1U << 3) /* transmitter enable */
+#define CONTROL_RE (1U << 2) /* receiver enable */
+
+#define MAC_ADDRHIGH 0x0004 /* high 16 bits of station address */
+
+#define MAC_ADDRLOW 0x0008 /* low 32 bits of station address */
+
+#define MAC_HASHHIGH 0x000c /* high 32 bits of multicast hash */
+
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