[src/nathanw_sa]: src/sys/arch/mips/alchemy/dev Add a slightly modified dev/i...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/452988afff25
branches:  nathanw_sa
changeset: 506071:452988afff25
user:      simonb <simonb%NetBSD.org@localhost>
date:      Mon Jul 29 15:42:43 2002 +0000

description:
Add a slightly modified dev/ic/com.c that supports the Alchemy
Semiconductor Au1x00 series on-chip UARTs.  Will be merged with
the original com.c driver once a few issues are tidied up.  Main
differences from a standard 16550 UART are:
 - separate rxdata and txdata registers
 - single 16-bit register for the clock divisor
 - "enable uart" register

diffstat:

 sys/arch/mips/alchemy/dev/aucomreg.h |  41 ++++++++++++++++++++++++++++++++++++
 sys/arch/mips/alchemy/dev/aucomvar.h |  29 +++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 0 deletions(-)

diffs (78 lines):

diff -r f7d41735f11a -r 452988afff25 sys/arch/mips/alchemy/dev/aucomreg.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/dev/aucomreg.h      Mon Jul 29 15:42:43 2002 +0000
@@ -0,0 +1,41 @@
+/* $NetBSD: aucomreg.h,v 1.1.2.2 2002/07/29 15:42:43 simonb Exp $ */
+
+/* copyright */
+
+#include <dev/ic/comreg.h>
+
+#undef com_data                /* XXX ... */
+#undef com_dlbl
+#undef com_dlbh
+#undef com_ier
+#undef com_iir
+#undef com_fifo
+#undef com_lctl
+#undef com_cfcr
+#undef com_mcr
+#undef com_lsr
+#undef com_msr
+#undef com_scratch
+
+#undef COM_FREQ        /* relative to CPU clock speed on Au1X00 */
+
+/*
+ * Alchemy Semi Au1X00 UART registers
+ */
+
+#define        com_rxdata      0x00    /* receive data register (R) */
+#define        com_txdata      0x04    /* transmit data register (W) */
+#define        com_ier         0x08    /* interrupt enable (R/W) */
+#define        com_iir         0x0c    /* interrupt identification (R) */
+#define        com_fifo        0x10    /* FIFO control (R/W) */
+#define        com_lctl        0x14    /* line control register (R/W) */
+#define        com_cfcr        0x14    /* line control register (R/W) */
+#define        com_mcr         0x18    /* modem control register (R/W) */
+#define        com_lsr         0x1c    /* line status register (R) */
+#define        com_msr         0x20    /* modem status register (R) */
+#define        com_dlb         0x28    /* divisor latch (16bit) (R/W) */
+#define        com_modctl      0x100   /* module control register (R/W) */
+
+/* XXX ISA-specific. */
+#undef COM_NPORTS
+#define        COM_NPORTS      0x104
diff -r f7d41735f11a -r 452988afff25 sys/arch/mips/alchemy/dev/aucomvar.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/dev/aucomvar.h      Mon Jul 29 15:42:43 2002 +0000
@@ -0,0 +1,29 @@
+/* $NetBSD: aucomvar.h,v 1.1.2.2 2002/07/29 15:42:43 simonb Exp $ */
+
+/* copyright */
+
+/* Renamed externally visible functions */
+#define        com_attach_subr aucom_attach_subr
+#define        comintr         aucomintr
+#define        comcnattach     aucomcnattach
+#define        com_is_console  aucom_is_console
+#define        com_kgdb_attach aucom_kgdb_attach
+
+#define        comprobe1       xxx_aucomprobe1         /* unused */
+#define        com_detach      xxx_aucom_detach        /* unused */
+#define        com_activate    xxx_aucom_activate      /* unused */
+
+/* Renamed externally visible variables */
+#define        comcons         aucomcons
+#define        com_cd          aucom_cd
+#define        com_rbuf_size   aucom_rbuf_size
+#define        com_rbuf_hiwat  aucom_rbuf_hiwat
+#define        com_rbuf_lowat  aucom_rbuf_lowat
+#define        com_debug       aucom_debug
+
+#include <dev/ic/comvar.h>
+
+#undef COM_MPLOCK      /* just in case... */
+#undef COM_DEBUG
+#undef COM_HAYESP
+#undef COM16650