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[src/trunk]: src/sys/arch/arm/arm Use 'p15' consistently in all mcr and mrc i...
details: https://anonhg.NetBSD.org/src/rev/65cfdd9b32cf
branches: trunk
changeset: 516193:65cfdd9b32cf
user: rearnsha <rearnsha%NetBSD.org@localhost>
date: Thu Oct 18 10:30:34 2001 +0000
description:
Use 'p15' consistently in all mcr and mrc instructions.
Fix warnings in stm/ldm instructions of get_pc_str_offset.
diffstat:
sys/arch/arm/arm/cpufunc_asm.S | 360 ++++++++++++++++++++--------------------
1 files changed, 180 insertions(+), 180 deletions(-)
diffs (truncated from 887 to 300 lines):
diff -r 589a8b2e4b53 -r 65cfdd9b32cf sys/arch/arm/arm/cpufunc_asm.S
--- a/sys/arch/arm/arm/cpufunc_asm.S Thu Oct 18 09:26:16 2001 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm.S Thu Oct 18 10:30:34 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm.S,v 1.8 2001/09/16 08:51:17 chris Exp $ */
+/* $NetBSD: cpufunc_asm.S,v 1.9 2001/10/18 10:30:34 rearnsha Exp $ */
/*
* xscale support code Copyright (c) 2001 Matt Thomas
@@ -69,19 +69,19 @@
*/
ENTRY(cpufunc_id)
- mrc 15, 0, r0, c0, c0, 0
+ mrc p15, 0, r0, c0, c0, 0
mov pc, lr
ENTRY(cpu_get_control)
- mrc 15, 0, r0, c1, c0, 0
+ mrc p15, 0, r0, c1, c0, 0
mov pc, lr
ENTRY(cpufunc_faultstatus)
- mrc 15, 0, r0, c5, c0, 0
+ mrc p15, 0, r0, c5, c0, 0
mov pc, lr
ENTRY(cpufunc_faultaddress)
- mrc 15, 0, r0, c6, c0, 0
+ mrc p15, 0, r0, c6, c0, 0
mov pc, lr
@@ -97,11 +97,11 @@
*/
/*ENTRY(cpufunc_control)
- mcr 15, 0, r0, c1, c0, 0
+ mcr p15, 0, r0, c1, c0, 0
mov pc, lr*/
ENTRY(cpufunc_domains)
- mcr 15, 0, r0, c3, c0, 0
+ mcr p15, 0, r0, c3, c0, 0
mov pc, lr
/*
@@ -115,46 +115,46 @@
*/
ENTRY(cpufunc_control)
- mrc 15, 0, r3, c1, c0, 0 /* Read the control register */
+ mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there is a change */
- mcrne 15, 0, r2, c1, c0, 0 /* Write new control register */
+ mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
mov r0, r3 /* Return old value */
mov pc, lr
#ifdef CPU_ARM3
/* The ARM3 has its control register in a different place. */
ENTRY(arm3_control)
- mrc 15, 0, r3, c2, c0, 0 /* Read the control register */
+ mrc p15, 0, r3, c2, c0, 0 /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there is a change */
- mcrne 15, 0, r2, c2, c0, 0 /* Write new control register */
+ mcrne p15, 0, r2, c2, c0, 0 /* Write new control register */
mov r0, r3 /* Return old value */
mov pc, lr
#endif
#ifdef CPU_ARM8
ENTRY(arm8_clock_config)
- mrc 15, 0, r3, c15, c0, 0 /* Read the clock register */
+ mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */
bic r2, r3, #0x11 /* turn off dynamic clocking
and clear L bit */
- mcr 15, 0, r2, c15, c0, 0 /* Write clock register */
+ mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
bic r2, r2, #0x10 /* clear the L bit */
bic r1, r2, #0x01 /* still keep dynamic clocking off */
- mcr 15, 0, r1, c15, c0, 0 /* Write clock register */
+ mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
mov r0, r0 /* NOP */
mov r0, r0 /* NOP */
mov r0, r0 /* NOP */
mov r0, r0 /* NOP */
- mcr 15, 0, r2, c15, c0, 0 /* Write clock register */
+ mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
mov r0, r3 /* Return old value */
mov pc, lr
#endif /* CPU_ARM8 */
@@ -170,16 +170,16 @@
* We need to flush the cache as it uses virtual addresses that
* are about to change
*/
- mcr 15, 0, r0, c7, c0, 0
+ mcr p15, 0, r0, c7, c0, 0
/* Write the TTB */
- mcr 15, 0, r0, c2, c0, 0
+ mcr p15, 0, r0, c2, c0, 0
/* If we have updated the TTB we must flush the TLB */
- mcr 15, 0, r0, c5, c0, 0
+ mcr p15, 0, r0, c5, c0, 0
/* For good measure we will flush the IDC as well */
- mcr 15, 0, r0, c7, c0, 0
+ mcr p15, 0, r0, c7, c0, 0
/* Make sure that pipeline is emptied */
mov r0, r0
@@ -219,16 +219,16 @@
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(arm8_cache_cleanID)
ldmfd sp!, {r0-r3, lr}
- mcr 15, 0, r0, c7, c7, 0 /* flush I+D cache */
+ mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
/* Write the TTB */
- mcr 15, 0, r0, c2, c0, 0
+ mcr p15, 0, r0, c2, c0, 0
/* If we have updated the TTB we must flush the TLB */
- mcr 15, 0, r0, c8, c7, 0
+ mcr p15, 0, r0, c8, c7, 0
/* For good measure we will flush the IDC as well */
- mcr 15, 0, r0, c7, c7, 0
+ mcr p15, 0, r0, c7, c7, 0
/* Make sure that pipeline is emptied */
mov r0, r0
@@ -260,17 +260,17 @@
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(sa110_cache_cleanID)
ldmfd sp!, {r0-r3, lr}
- mcr 15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
- mcr 15, 0, r0, c7, c10, 4 /* drain write (& fill) buffer */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
+ mcr p15, 0, r0, c7, c10, 4 /* drain write (& fill) buffer */
/* Write the TTB */
- mcr 15, 0, r0, c2, c0, 0 /* set translation table base */
+ mcr p15, 0, r0, c2, c0, 0 /* set translation table base */
/* If we have updated the TTB we must flush the TLB */
- mcr 15, 0, r0, c8, c7, 0 /* invalidate I&D TLB */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate I&D TLB */
/* The cleanID above means we only need to flush the I cache here */
- mcr 15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
/* Make sure that pipeline is emptied */
mov r0, r0
@@ -299,20 +299,20 @@
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(xscale_cache_cleanID)
ldmfd sp!, {r0-r3, lr}
- mcr 15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
- mcr 15, 0, r0, c7, c10, 4 /* drain write (& fill) buffer */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
+ mcr p15, 0, r0, c7, c10, 4 /* drain write (& fill) buffer */
/* Write the TTB */
- mcr 15, 0, r0, c2, c0, 0 /* set translation table base */
+ mcr p15, 0, r0, c2, c0, 0 /* set translation table base */
/* If we have updated the TTB we must flush the TLB */
- mcr 15, 0, r0, c8, c7, 0 /* invalidate I&D TLB */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate I&D TLB */
/* The cleanID above means we only need to flush the I cache here */
- mcr 15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
/* Make sure that pipeline is emptied */
- mrc 15, 0, r0, c2, c0, 0 /* read some register in CP15 */
+ mrc p15, 0, r0, c2, c0, 0 /* read some register in CP15 */
mov r0, r0 /* for the read to complete */
sub pc, pc, #4 /* branch to next instruction */
/* (flush the instruction pipeline) */
@@ -330,11 +330,11 @@
#if defined(CPU_ARM6) || defined(CPU_ARM7)
ENTRY(arm67_tlb_flush)
- mcr 15, 0, r0, c5, c0, 0
+ mcr p15, 0, r0, c5, c0, 0
mov pc, lr
ENTRY(arm67_tlb_purge)
- mcr 15, 0, r0, c6, c0, 0
+ mcr p15, 0, r0, c6, c0, 0
mov pc, lr
#endif /* CPU_ARM6 || CPU_ARM7 */
@@ -350,48 +350,48 @@
#endif
#ifdef CPU_ARM8
ENTRY(arm8_tlb_flushID)
- mcr 15, 0, r0, c8, c7, 0 /* flush I+D tlb */
+ mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
mov pc, lr
ENTRY(arm8_tlb_flushID_SE)
- mcr 15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
+ mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
mov pc, lr
#endif /* CPU_ARM8 */
#if defined(CPU_SA110) || defined(CPU_XSCALE)
ENTRY_NP(xscale_tlb_flushID)
ENTRY(sa110_tlb_flushID)
- mcr 15, 0, r0, c8, c7, 0 /* flush I+D tlb */
+ mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
mov pc, lr
#if defined(CPU_SA110)
ENTRY(sa110_tlb_flushID_SE)
- mcr 15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
- mcr 15, 0, r0, c8, c5, 0 /* flush I tlb */
+ mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
+ mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
mov pc, lr
#endif /* CPU_SA110 */
#if defined(CPU_XSCALE)
ENTRY(xscale_tlb_flushID_SE)
- mcr 15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
- mcr 15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
- mcr 15, 0, r0, c7, c5, 6 /* inv. branch target buffer */
+ mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
+ mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
+ mcr p15, 0, r0, c7, c5, 6 /* inv. branch target buffer */
mov pc, lr
#endif /* CPU_XSCALE */
ENTRY_NP(xscale_tlb_flushI)
ENTRY(sa110_tlb_flushI)
- mcr 15, 0, r0, c8, c5, 0 /* flush I tlb */
+ mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
mov pc, lr
ENTRY_NP(xscale_tlb_flushD)
ENTRY(sa110_tlb_flushD)
- mcr 15, 0, r0, c8, c6, 0 /* flush D tlb */
+ mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
mov pc, lr
ENTRY_NP(xscale_tlb_flushD_SE)
ENTRY(sa110_tlb_flushD_SE)
- mcr 15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
+ mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
mov pc, lr
#endif /* CPU_SA110 || CPU_XSCALE */
@@ -401,13 +401,13 @@
#if defined(CPU_ARM3)
ENTRY(arm3_cache_flush)
- mcr 15, 0, r0, c1, c0, 0
+ mcr p15, 0, r0, c1, c0, 0
mov pc, lr
#endif /* CPU_ARM3 */
#if defined(CPU_ARM6) || defined(CPU_ARM7)
ENTRY(arm67_cache_flush)
- mcr 15, 0, r0, c7, c0, 0
+ mcr p15, 0, r0, c7, c0, 0
mov pc, lr
#endif /* CPU_ARM6 || CPU_ARM7 */
@@ -425,11 +425,11 @@
#ifdef CPU_ARM8
ENTRY(arm8_cache_flushID)
- mcr 15, 0, r0, c7, c7, 0 /* flush I+D cache */
+ mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
mov pc, lr
ENTRY(arm8_cache_flushID_E)
- mcr 15, 0, r0, c7, c7, 1 /* flush I+D single entry */
+ mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
mov pc, lr
ENTRY(arm8_cache_cleanID)
@@ -437,37 +437,37 @@
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