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[src/trunk]: src/sys/arch/arm Add support calls for ARM9.
details: https://anonhg.NetBSD.org/src/rev/7db73d8d8526
branches: trunk
changeset: 516202:7db73d8d8526
user: rearnsha <rearnsha%NetBSD.org@localhost>
date: Thu Oct 18 14:10:07 2001 +0000
description:
Add support calls for ARM9.
Where ARM9, StrongARM and XScale share the same function, rename it
as armv4_XXX.
diffstat:
sys/arch/arm/arm/cpufunc.c | 137 ++++++++++++++++++++++++++++++++++++++--
sys/arch/arm/arm/cpufunc_asm.S | 115 ++++++++++++++++++++++++++++++----
sys/arch/arm/include/cpufunc.h | 49 ++++++++++---
3 files changed, 266 insertions(+), 35 deletions(-)
diffs (truncated from 472 to 300 lines):
diff -r a577d5147e73 -r 7db73d8d8526 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Thu Oct 18 14:03:43 2001 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Thu Oct 18 14:10:07 2001 +0000
@@ -1,9 +1,10 @@
-/* $NetBSD: cpufunc.c,v 1.11 2001/07/09 19:51:14 reinoud Exp $ */
+/* $NetBSD: cpufunc.c,v 1.12 2001/10/18 14:10:07 rearnsha Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
* arm8 support code Copyright (c) 1997 ARM Limited
* arm8 support code Copyright (c) 1997 Causality Limited
+ * arm9 support code Copyright (C) 2001 ARM Ltd
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
@@ -409,6 +410,76 @@
};
#endif /* CPU_ARM8 */
+#ifdef CPU_ARM9
+struct cpu_functions arm9_cpufuncs = {
+ /* CPU functions */
+
+ cpufunc_id, /* id */
+
+ /* MMU functions */
+
+ cpufunc_control, /* control */
+ cpufunc_domains, /* Domain */
+ arm9_setttb, /* Setttb */
+ cpufunc_faultstatus, /* Faultstatus */
+ cpufunc_faultaddress, /* Faultaddress */
+
+ /* TLB functions */
+
+ armv4_tlb_flushID, /* tlb_flushID */
+ arm9_tlb_flushID_SE, /* tlb_flushID_SE */
+ armv4_tlb_flushI, /* tlb_flushI */
+ (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
+ armv4_tlb_flushD, /* tlb_flushD */
+ armv4_tlb_flushD_SE, /* tlb_flushD_SE */
+
+ /* Cache functions */
+
+ arm9_cache_flushID, /* cache_flushID */
+ arm9_cache_flushID_SE, /* cache_flushID_SE */
+ arm9_cache_flushI, /* cache_flushI */
+ arm9_cache_flushI_SE, /* cache_flushI_SE */
+ arm9_cache_flushD, /* cache_flushD */
+ arm9_cache_flushD_SE, /* cache_flushD_SE */
+
+ /* ... lets use the cache in write-through mode. */
+ arm9_cache_cleanID, /* cache_cleanID */
+ (void *)arm9_cache_cleanID, /* cache_cleanID_SE */
+ arm9_cache_cleanID, /* cache_cleanD */
+ (void *)arm9_cache_cleanID, /* cache_cleanD_SE */
+
+ arm9_cache_flushID, /* cache_purgeID */
+ arm9_cache_flushID_SE, /* cache_purgeID_SE */
+ arm9_cache_flushD, /* cache_purgeD */
+ arm9_cache_flushD_SE, /* cache_purgeD_SE */
+
+ /* Other functions */
+
+ cpufunc_nullop, /* flush_prefetchbuf */
+ armv4_drain_writebuf, /* drain_writebuf */
+ cpufunc_nullop, /* flush_brnchtgt_C */
+ (void *)cpufunc_nullop, /* flush_brnchtgt_E */
+
+ (void *)cpufunc_nullop, /* sleep */
+
+ /* Soft functions */
+ arm9_cache_syncI, /* cache_syncI */
+ (void *)arm9_cache_cleanID, /* cache_cleanID_rng */
+ (void *)arm9_cache_cleanID, /* cache_cleanD_rng */
+ arm9_cache_flushID_rng, /* cache_purgeID_rng */
+ arm9_cache_flushD_rng, /* cache_purgeD_rng */
+ arm9_cache_syncI_rng, /* cache_syncI_rng */
+
+ cpufunc_null_fixup, /* dataabt_fixup */
+ cpufunc_null_fixup, /* prefetchabt_fixup */
+
+ arm9_context_switch, /* context_switch */
+
+ arm9_setup /* cpu setup */
+
+};
+#endif /* CPU_ARM9 */
+
#ifdef CPU_SA110
struct cpu_functions sa110_cpufuncs = {
/* CPU functions */
@@ -425,12 +496,12 @@
/* TLB functions */
- sa110_tlb_flushID, /* tlb_flushID */
+ armv4_tlb_flushID, /* tlb_flushID */
sa110_tlb_flushID_SE, /* tlb_flushID_SE */
- sa110_tlb_flushI, /* tlb_flushI */
- (void *)sa110_tlb_flushI, /* tlb_flushI_SE */
- sa110_tlb_flushD, /* tlb_flushD */
- sa110_tlb_flushD_SE, /* tlb_flushD_SE */
+ armv4_tlb_flushI, /* tlb_flushI */
+ (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
+ armv4_tlb_flushD, /* tlb_flushD */
+ armv4_tlb_flushD_SE, /* tlb_flushD_SE */
/* Cache functions */
@@ -454,7 +525,7 @@
/* Other functions */
cpufunc_nullop, /* flush_prefetchbuf */
- sa110_drain_writebuf, /* drain_writebuf */
+ armv4_drain_writebuf, /* drain_writebuf */
cpufunc_nullop, /* flush_brnchtgt_C */
(void *)cpufunc_nullop, /* flush_brnchtgt_E */
@@ -540,6 +611,14 @@
return 0;
}
#endif /* CPU_ARM8 */
+#ifdef CPU_ARM9
+ if (cputype == CPU_ID_ARM920T) {
+ pte_cache_mode = PT_C; /* Select write-through cacheing. */
+ cpufuncs = arm9_cpufuncs;
+ cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
+ return 0;
+ }
+#endif /* CPU_ARM9 */
#ifdef CPU_SA110
if (cputype == CPU_ID_SA110 || cputype == CPU_ID_SA1100 ||
cputype == CPU_ID_SA1110) {
@@ -951,7 +1030,7 @@
*/
#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
- defined(CPU_ARM8) || defined(CPU_SA110)
+ defined(CPU_ARM8) || defined (CPU_ARM9) || defined(CPU_SA110)
int cpuctrl;
#define IGN 0
@@ -1200,6 +1279,48 @@
}
#endif /* CPU_ARM8 */
+#ifdef CPU_ARM9
+struct cpu_option arm9_options[] = {
+ { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
+ { "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
+ { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
+ { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
+ { "arm9.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
+ { NULL, IGN, IGN, 0 }
+};
+
+void
+arm9_setup(args)
+ char *args;
+{
+ int cpuctrlmask;
+
+ cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
+ | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE;
+ cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
+ | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
+ | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+ | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
+ | CPU_CONTROL_CPCLK;
+
+ cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl);
+
+ /* Clear out the cache */
+ cpu_cache_purgeID();
+
+ /* Set the control register */
+ cpu_control(0xffffffff, cpuctrl);
+
+}
+#endif /* CPU_ARM9 */
+
#ifdef CPU_SA110
struct cpu_option sa110_options[] = {
#ifdef COMPAT_12
diff -r a577d5147e73 -r 7db73d8d8526 sys/arch/arm/arm/cpufunc_asm.S
--- a/sys/arch/arm/arm/cpufunc_asm.S Thu Oct 18 14:03:43 2001 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm.S Thu Oct 18 14:10:07 2001 +0000
@@ -1,10 +1,11 @@
-/* $NetBSD: cpufunc_asm.S,v 1.9 2001/10/18 10:30:34 rearnsha Exp $ */
+/* $NetBSD: cpufunc_asm.S,v 1.10 2001/10/18 14:10:07 rearnsha Exp $ */
/*
* xscale support code Copyright (c) 2001 Matt Thomas
* arm7tdmi support code Copyright (c) 2001 John Fremlin
* arm8 support code Copyright (c) 1997 ARM Limited
* arm8 support code Copyright (c) 1997 Causality Limited
+ * arm9 support code Copyright (C) 2001 ARM Limited
* Copyright (c) 1997,1998 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
@@ -238,6 +239,20 @@
mov pc, lr
#endif /* CPU_ARM8 */
+#ifdef CPU_ARM9
+ENTRY(arm9_setttb)
+ /*
+ * Since we use the caches in write-through mode, we only have to
+ * drain the write buffers and flush the caches.
+ */
+ mcr p15, 0, r0, c7, c7, 0 /* Flush I+D Caches */
+ mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
+
+ mcr p15, 0, r0, c2, c0, 0 /* Load new ttb */
+
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+ mov pc, lr
+#endif /* CPU_ARM9 */
#if defined(CPU_SA110) || defined(CPU_XSCALE)
Lblock_userspace_access:
@@ -358,9 +373,8 @@
mov pc, lr
#endif /* CPU_ARM8 */
-#if defined(CPU_SA110) || defined(CPU_XSCALE)
-ENTRY_NP(xscale_tlb_flushID)
-ENTRY(sa110_tlb_flushID)
+#if defined (CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE)
+ENTRY(armv4_tlb_flushID)
mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
mov pc, lr
@@ -371,6 +385,13 @@
mov pc, lr
#endif /* CPU_SA110 */
+#if defined(CPU_ARM9)
+ENTRY(arm9_tlb_flushID_SE)
+ mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
+ mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
+ mov pc, lr
+#endif
+
#if defined(CPU_XSCALE)
ENTRY(xscale_tlb_flushID_SE)
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
@@ -379,21 +400,18 @@
mov pc, lr
#endif /* CPU_XSCALE */
-ENTRY_NP(xscale_tlb_flushI)
-ENTRY(sa110_tlb_flushI)
+ENTRY(armv4_tlb_flushI)
mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
mov pc, lr
-ENTRY_NP(xscale_tlb_flushD)
-ENTRY(sa110_tlb_flushD)
+ENTRY(armv4_tlb_flushD)
mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
mov pc, lr
-ENTRY_NP(xscale_tlb_flushD_SE)
-ENTRY(sa110_tlb_flushD_SE)
+ENTRY(armv4_tlb_flushD_SE)
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
mov pc, lr
-#endif /* CPU_SA110 || CPU_XSCALE */
+#endif /* CPU_ARM9 || CPU_SA110 || CPU_XSCALE */
/*
* Cache functions
@@ -576,6 +594,38 @@
mov pc, lr
#endif /* CPU_ARM8 */
+#ifdef CPU_ARM9
+ENTRY(arm9_cache_flushID)
+ mcr p15, 0, r0, c7, c7, 0 /* Flush I+D cache */
+ mov pc, lr
+
+ENTRY(arm9_cache_flushID_SE)
+ mcr p15, 0, r0, c7, c5, 1 /* Flush one entry from I cache */
+ mcr p15, 0, r0, c7, c6, 1 /* Flush one entry from D cache */
+ mov pc, lr
+
+ENTRY(arm9_cache_flushI)
+ mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
+ mov pc, lr
+
+ENTRY(arm9_cache_flushI_SE)
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