Re: CVS commit: src/sys/arch

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

> Module Name:	src
> Committed By:	skrll
> Date:		Thu Sep 23 06:34:00 UTC 2021
> 
> Modified Files:
> 	src/sys/arch/aarch64/aarch64: cpufunc.c
> 	src/sys/arch/arm/arm32: cpu.c
> 
> Log Message:
> Print the cache information in similar formats and arm and aarch64, e.g.
 :
> aarch64 before
> [   1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
> [   1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
> [   1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache
> 
> aarch64 after
> [   1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
> [   1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
> [   1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache

I prefer "line(s)" as before rather than "set(s)" since
the latter implies "N-way set associative cache".

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Izumi Tsutsui