Re: NetBSD in SIMH vax with 512 MB RAM

[Mouse <mouse%Rodents-Montreal.ORG@localhost>]

> Or else you could just say that as soon as anything is set to an
> undefined behavior, the whole machine is just undefined everywhere,
> and you can start interpreting instructions as 6502 opcodes.

As far as the formal spec goes, I think that's pretty much what it
says.  Note that there is text that specifically says that if the
scalar processor's operation goes UNDEFINED, so does the vector
processor's, if any - even if the source of the UNDEFINED scalar
processor opration has nothing obvious to do with the vector processor.
(This text is in chapter 1, page 1-2, where it talks about UNDEFINED
and UNPREDICTABLE behaviour.)

> I guess in a sense, that would be within the specs, but hardly a
> useful interpretation.

That particular example, yes.  But, for example, if it saves some
gates, I could see a hardware designer simply merging all of
80000000-ffffffff into a single space, with SLR as its length register.
Provided SLR is in range, this is operationally identical, and if SLR
is out of range, then anything goes anyway.

>> Yeah.  I wonder what's behind it.  [...]
> You could also ask why P0LR<26:24> are ignored.  Same story.

!!  I missed that.  Thank you for pointing it out.

If anything, that one is even stranger.  The sign bit, that at least
could make a tiny, if twisted, bit of sense.  But the 0x07000000 bits?
That's just bizarre.

The only other place I see bits 26:24 of anything mentioned is that
they're the ASTLVL bits in the PSL.  But I have trouble imagining DEC
caring about software that confuses PSL with P0LR, quite aside from all
the other reasons I have trouble seeing that as relevant.

> I have no clue about that, and find it incredibly strange.

Agreed!  (And my VAX emulator has a couple of bugs for me to fix.)

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