> The 1GB limit is because of the layout of the registers for the
> memory mapping. [21 bits for the PFN in a PTE]
> This got an update on the NVAX, where a different format PTE was
> defined, in which you have 25 bits for the address. [...]
> As for the division between memory and I/O space, I guess it could
> have been done differently on different implementations, but the
> complexity it would have implied in software if that had been done
> was probably not something DEC wanted. So in all machines I've ever
> looked at, the I/O space starts at 512M. Physical memory is always
> below that.
What happens for machines that have more than 512M of physical memory
(like that 7000 at LSSM)? It can't _all_ be below the 512M point!
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