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Re: New Vax - future directions :-)

On 2021-07-07 04:15, Mouse wrote:
It's really just the instructions that deals with quads
...or octawords; there's no ASHO, but there are CLRO and MOVO (and
MOVAO and PUSHAO, which appear to be less upsetting).
There is no CLRO or MOVO. I checked. :-)

Maybe not in some VAXen, or some versions of the VARM.  But they're in
the VARM as of EL-00032-00-decStd32_Jan90.  CLRO is 7CFD, on page 3-14
along with CLRB, CLRW, CLRL, and CLRQ, and MOVO is 7DFD, on page 3-25
along with MOVB, MOVW, MOVL, and MOVQ.  (7CFD is also CLRH on page
3-123; MOVH is 70FD, on 3-134, not the same as MOVO.)

MOVO, MOVH, and CLRO/CLRH _are_ in an optional instruction group, but
they're well-defined.

ARGH! I *knew* I should have checked more. Yes, I checked the old VARM as well as the processor handbook from 1982.

Very sorry. :-(

Well, CLRO clearly can be identical to CLRH, since they will do exactly the same (same with D-float and quad). The MOV(s) can't be shared, since the FP MOVs are expected to cause FP exceptions for some valua.

But I do agree it is a bit of a problem in that it's an implied
register reference that is slightly different, and which clearly
should change some if we were to extend the size of the registers.

Well, there's a slight subtlety.

CLRQ is two things on VAX-32, and they do not map to the same thing on
VAX-64.  CLRQ is both "clear 64-bit datum" and "clear double-word
datum", and those are no longer the same thing on VAX-64.  Given the
way the naming conventions are set up, I think the name CLRQ should be
attached to the 64-bit - single-word - operation on VAX-64.

I agree. The clear double-(long)word thingy is sortof the problem, since it's an effect of the fact that a register isn't that long. But the instruction implies 64-bits, and I think this is the more important aspect.

It's possibly arguable that there should be a CLRR or some such, taking
a .rw operand and clearing all registers that correspond to set bits in
the operand, likely with a reserved operand fault if the 0x8000 bit is
set.  But that's probably unwarranted tinkering with the instruction
set, like various other instructions I'd kinda like to see but probably
won't, such as FLS, FLC, COUNT, and ALU, though admittedly CLRR feels
less VAXy than the others, in that instructions that work only on
registers are relatively rare.

You do have PUSHR and POPR, which falls in exactly the same category...


Johnny Billquist                  || "I'm on a bus
                                  ||  on a psychedelic trip
email: bqt%softjar.se@localhost             ||  Reading murder books
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