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Re: New Vax - future directions :-)
>> The idea that an operation that takes a single register as an argument woul$
That's certainly a defensible position. I'm not sure whether I agree.
I see arguments each way.
But I'm curious: what's the difference between CLRQ R0 (operates on R1
as well) and PUSHL R0 (operates on SP as well)? Does PUSHL upset you
too, and, if not, why the difference? (I see plenty of possible
reasons; I'm curious about yours. If, that is, PUSHL doesn't bother
Would you feel better if the assembler syntax were "CLRQ R0-R1" or some
Does it also bother you that 3/4 of the bytes that exist in registers
are not accessible using byte instructions? Why or why not?
> [...] CLRQ [...] MOVQ
> But I think those are the only ones defined that I can think of.
Among explicitly-quadword instructions, I think the only other one in
EL-00032-00-decStd32_Jan90 is ASHQ. (There are two other instructions
that are quadword variants of instructions that exist for other sizes,
MOVAQ and PUSHAQ, but they are address-of instructions, not involving
materialized quadword data.)
But there are also EMUL and EDIV, which glue two registers together
into a 64-bit operand. In each case (CLRQ, MOVQ, ASHQ, EMUL, EDIV),
when the 64-bit operand is in registers, it is in two adjacent
registers and only the lower-numbered one appears as an explicit
operand in the instruction stream.
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